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Ask HN: Resources for general purpose GPU development on Apple's M* chips?

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Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#21

Post by selimthegrim »

nixpulvis wrote: post #13
rgovostes wrote: post #12

It's hard to answer not knowing exactly what your aim is, or your experience level with CUDA and how easily the concepts you know will map to Metal, and what you find "restricted and convoluted" about the documentation. helped me write some simple Metal-accelerated code by scaffolding the compute pipeline, which took most of the nuisance out of learning the API and let me focus on writing the kernel code. Here's the…

2024 and still finding cheat codes in Tony Hawk Pro Skater 2. Wild!

If Jamie Kennedy is reading this, we still haven’t found the cheat code to make you funny.

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#22

Post by KeplerBoy »

morphle wrote: post #20
KeplerBoy wrote: post #16

Earlier quoted context omitted.

Where does the 270 gbit/s networking figure come from? Is it the aggregate bandwidth from the pcie slots on the mac pro, which could support nics at that speeds (and above according to my quick maths#), but there is not really any driver support for modern Intel or Mellanox/Nvidia NICs as far as I can tell. My use case would be hooking up a device which spews out sensor data at 100 gbit/s over qsfp28 ethernet as dire…

> Where does the 270 gbit/s networking figure come from? Is it the aggregate bandwidth from the pcie slots on the Mac pro We both should restate and specify the calculation for each different Apple Silicon chip and the PCB/machine model it is wired onto. The $599 M4 Mac mini base model networking (aggregated Wifi, USB-C, 10G Ethernet, Thunderbolt PCIe) is almost 270 Gbps. Your 720 Gbps is for a >$8000 Mac Pro M2 Ultr…

The pcie configuration was taken from the mac pro and it's m2 ultra. https://www.apple.com/mac-pro/

I'd assume the mac mini has a less extensive pcie/tb subsystem.

No idea what people are doing with all those pcie slots except for nvme cards. I wonder how hard it would be to talk to a pcie fpga.

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#23

Post by twoodfin »

dgfitz wrote: post #17
morphle wrote: post #7

You can help with the reverse engineering of Apple Silicon done by a dozen people worldwide, that is how we find out the GPU and NPU instructions[1-4]. There is over 43 trillion float operations per second to unlock at 8 terabit per second 'unified' memory bandwidth and 270 gigabits per second networking (less on the smaller chips).... [1] https://github.com/AsahiLinux/gpu [2] https://github.com/dougallj/applegpu [3]…

It’s too bad they don’t make this easier on developers, Apple. Is there a reason I don’t see?

Apple wants total freedom to rework lower levels of the stack down to the hardware, without worrying about application compatibility, hence their answer will continue to be Metal.

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#24

Post by morphle »

KeplerBoy wrote: post #22
morphle wrote: post #20

Earlier quoted context omitted.

> Where does the 270 gbit/s networking figure come from? Is it the aggregate bandwidth from the pcie slots on the Mac pro We both should restate and specify the calculation for each different Apple Silicon chip and the PCB/machine model it is wired onto. The $599 M4 Mac mini base model networking (aggregated Wifi, USB-C, 10G Ethernet, Thunderbolt PCIe) is almost 270 Gbps. Your 720 Gbps is for a >$8000 Mac Pro M2 Ultr…

The pcie configuration was taken from the mac pro and it's m2 ultra. https://www.apple.com/mac-pro/ I'd assume the mac mini has a less extensive pcie/tb subsystem. No idea what people are doing with all those pcie slots except for nvme cards. I wonder how hard it would be to talk to a pcie fpga.

You use SerDes high speed serial links (up to 224 Gbps in 2025) to communicate between chips. A PCIe lane is just a Serdes with a 30% packet protocol overhead that uses DMA to copy bytes between to SRAM or DRAM buffers.

You aggregate PCIe lanes (x16, x8, x4/Thunderbolt, x1). You could also built mesh networks from SerDes but now instead of PCIe switches You would need SerDes switches or routers (Ethernet, NVlink, Infiniband).

You need those high speed links between chips for much more than SSD/NVME cards. Other NAS, Processors, Ethernet/internet, Camera, Wifi, Optics, DRAM, SRAM, power etc. For intercore communication (between processors or between chiplets), between networked PCB's, between DRAM chips (DDR5 is just another SerDes protocol), Flash Chips, camera chips, etc. Any other chip at faster then 250 Mbps speeds.

I aggregate all the M4 Mac mini ports into a M4 cluster by mesh networking all its Serdes/PCIe with FPGAs into a very cheap low power supercomputer with exaflop performance. Cheaper than NVDIA. I'm sure Apple does the same in their data centers.

My talk [1] on Wafer Scale Integration and free space optics goes deeper into how and why SerDes and PCIe will be replaced by fiber optics and free space optics for power reasons. I'm sure several parallel 2 Ghz optic lambdas per fiber (but no SerDes!) will be the next step in Apple Silicon as well: the M4 power budget already is mostly in the off-chip SerDes/Thunderbolt networking links.

[1] https://vimeo.com/731037615

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#25

Post by aleinin »

If you're looking for a high level introduction to GPU development on Apple silicon I would recommend learning Metal. It's Apple's GPU acceleration language similar to CUDA for Nvidia hardware. I ported a set of puzzles for CUDA called GPU-Puzzles (a collection of exercises designed to teach GPU programming fundamentals)[1] to Metal [2]. I think it's a very accessible introduction to Metal and writing GPU kernels.

[1] https://github.com/srush/GPU-Puzzles

[2] https://github.com/abeleinin/Metal-Puzzles

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#26

Post by dylan604 »

aleinin wrote: post #25

If you're looking for a high level introduction to GPU development on Apple silicon I would recommend learning Metal. It's Apple's GPU acceleration language similar to CUDA for Nvidia hardware. I ported a set of puzzles for CUDA called GPU-Puzzles (a collection of exercises designed to teach GPU programming fundamentals)[1] to Metal [2]. I think it's a very accessible introduction to Metal and writing GPU kernels. [1…

After a quick scan through the [2] link, I have added this to the list of things to look into in 2025

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#27

Post by dylan604 »

morphle wrote: post #19
dgfitz wrote: post #17

Earlier quoted context omitted.

It’s too bad they don’t make this easier on developers, Apple. Is there a reason I don’t see?

There certainly is a reason and indeed you don't see it because Apple downplays these things in their PR. It might be the same reason that is behind NVDIA's CUDA moat. CUDA lock-in prevented competitors like AMD and Intel to convince programmers and their customers to switch away from CUDA. So there was no software ported to their competitive GPU's. So you get anti-trust lawsuits [1]. I think you should put yourself…

At this point, Apple is absolutely not afraid of an anti-trust lawsuit. To them, it is part of the cost of doing business

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#28

Post by morphle »

dylan604 wrote: post #27
morphle wrote: post #19

Earlier quoted context omitted.

There certainly is a reason and indeed you don't see it because Apple downplays these things in their PR. It might be the same reason that is behind NVDIA's CUDA moat. CUDA lock-in prevented competitors like AMD and Intel to convince programmers and their customers to switch away from CUDA. So there was no software ported to their competitive GPU's. So you get anti-trust lawsuits [1]. I think you should put yourself…

At this point, Apple is absolutely not afraid of an anti-trust lawsuit. To them, it is part of the cost of doing business

I concur, they are virtually untouchable in this respect. No one else will throw a trillion or more into developing lower power faster silicon.

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#29

Post by KeplerBoy »

morphle wrote: post #24
KeplerBoy wrote: post #22

Earlier quoted context omitted.

The pcie configuration was taken from the mac pro and it's m2 ultra. https://www.apple.com/mac-pro/ I'd assume the mac mini has a less extensive pcie/tb subsystem. No idea what people are doing with all those pcie slots except for nvme cards. I wonder how hard it would be to talk to a pcie fpga.

You use SerDes high speed serial links (up to 224 Gbps in 2025) to communicate between chips. A PCIe lane is just a Serdes with a 30% packet protocol overhead that uses DMA to copy bytes between to SRAM or DRAM buffers. You aggregate PCIe lanes (x16, x8, x4/Thunderbolt, x1). You could also built mesh networks from SerDes but now instead of PCIe switches You would need SerDes switches or routers (Ethernet, NVlink, Inf…

> I aggregate all the M4 Mac mini ports into a M4 cluster by mesh networking all its Serdes/PCIe with FPGAs into a very cheap low power supercomputer with exaflop performance. Cheaper than NVDIA. I'm sure Apple does the same in their data centers.

That sounds super interesting, do you happen to have some further information on that? Is it just a bunch of FPGAs issuing DMA TLPs?

Re: Ask HN: Resources for general purpose GPU development on Apple's M* chips?

#30

Post by morphle »

twoodfin wrote: post #23
dgfitz wrote: post #17

Earlier quoted context omitted.

It’s too bad they don’t make this easier on developers, Apple. Is there a reason I don’t see?

Apple wants total freedom to rework lower levels of the stack down to the hardware, without worrying about application compatibility, hence their answer will continue to be Metal.

I agree that it allows Apple to redefine Apple Silicon instruction sets without having do explain it to 3rd party software developers, but it is certainly not the main reason they hide the technical documentation of the chips.
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