> How the hell would you verify an AI-generated silicon design?
I think you're asking a different question, but in the context of the OP researchers are exploring AI for solving deterministic but intractable problems in the field of chip design and not generating designs end to end.
Here's an excerpt from the paper.
"The objective is to place
a netlist graph of macros (e.g., SRAMs) and standard cells
(logic gates, such as NAND, NOR, and XOR) onto a chip
canvas, such that power, performance, and area (PPA) are
optimized, while adhering to constraints on placement density and routing congestion (described in Sections 3.3.6
and 3.3.5). Despite decades of research on this problem,
it is still necessary for human experts to iterate for weeks
with the existing placement tools, in order to produce solutions that meet multi-faceted design criteria."
The hope is that Reinforcement Learning can find solutions to such complex optimization problems.