81–90 of 128 posts
"8K video recording" - does anyone really need this? Seems like for negligible gain in quality people are pushed to sacrifice their storage & battery, and so upgrade their hardware sooner...
I need more than 8K. I'm working at microscopic levels when I study minerals, I need as much resolution as I can possibly get, to the limit of optical diffraction.
Honest question. I hope I learn something about studying minerals!
The article doesn't properly explain how DRAM is different from SRAM. DRAM has to constantly refresh itself in order not to 'forget' its contents.
Why would we use DRAM, then? It seems better not to have to refresh it all the time. (I think I more or less know, but I’d rather talk about it than look it up this morning.)
The article doesn't properly explain how DRAM is different from SRAM. DRAM has to constantly refresh itself in order not to 'forget' its contents.
Why would we use DRAM, then? It seems better not to have to refresh it all the time. (I think I more or less know, but I’d rather talk about it than look it up this morning.)
One bit of DRAM is just one transistor and one capacitor. Massive density improvements; all the complexity is in the row/column circuitry at the edges of the array. And it only burns power during accesses or refreshes. If you don't need to refresh very often, you can get the power very low. If the array isn't being accessed, the refresh time can be double-digit milliseconds, perhaps triple-digit.
Which of course leads to problems like rowhammer, where rows affected by adjacent accesses don't get additional refreshes like they should (because this has a performance cost -- any cycle spent refreshing is a cycle not spent accessing), and you end up with the RAM reading out different bits than were put in. Which is the most fundamental defect conceivable for a storage device, but the industry is too addicted to performance to tap the brakes and address correctness. Every DDR3/DDR4 chip ever manufactured is defective by design.
Earlier quoted context omitted.
This is sort of the role that L3 cache plays already. Your proposal would be effectively an upgradable L4 cache. No idea if the economics on that are worth it vs bigger DRAM so you have less pressure on the nvme disk.
Cache is not general purpose as far as I know. I want to be able to do whatever I want with it.
There was briefly a product called vCage loading a whole secure hypervisor into cache-as-RAM, with a goal of being secure against DRAM-remanence ("cold-boot") attacks where the DIMMs are fast-chilled to slow charge leakage and removed from the target system to dump their contents. Since the whole secure perimeter was on-die in the CPU, it could use memory encryption to treat the DRAM as untrusted.
So, yeah, you can do it. It's funky.
Earlier quoted context omitted.
Last time I checked, DDR5 and DDR4 latency was basically the same. Very little progress there. May be with integrating DRAM and CPU on the same package, some latency wins will be available just because wires will be shorter, but nothing groundbreaking.
There's another factor, which is the number of independent channels; DDR5 doubles the number of channels per memory stick. This gets more important as CPUs get more and more cores.
Earlier quoted context omitted.
1080p looks different to 4k. Just because its 'plenty' doesn't mean 4k doesn't matter. And we are at 2024, i own a 4k lg oled display now for years. Why not leverage it? Just because 1080p is 'plenty'?
The problem with 4k, which 99% of people only experience as a stream, is that it's over-compressed. A 1080p BluRay is 36 Mbit. Netflix 4k is 15 Mbit. So unless I see people mentioning the media, I am always weary of the comparison.
The article doesn't properly explain how DRAM is different from SRAM. DRAM has to constantly refresh itself in order not to 'forget' its contents.
Why would we use DRAM, then? It seems better not to have to refresh it all the time. (I think I more or less know, but I’d rather talk about it than look it up this morning.)
I think the long and short of it is that DRAM is cheap. DRAM needs one transistor per data bit. Competing technologies needed far more. SRAM needed six transistors per bit for example.
Dennard figured out how to vastly cut down complexity, thus costs.
The article doesn't properly explain how DRAM is different from SRAM. DRAM has to constantly refresh itself in order not to 'forget' its contents.
Earlier quoted context omitted.
Why would we use DRAM, then? It seems better not to have to refresh it all the time. (I think I more or less know, but I’d rather talk about it than look it up this morning.)
Because SRAM is essentially a flipflop gate. It takes at least four transistors to store a single bit in SRAM, some designs use six. And current must continuously flow to keep the transistors in their state, so it's rather power hungry. One bit of DRAM is just one transistor and one capacitor. Massive density improvements; all the complexity is in the row/column circuitry at the edges of the array. And it only burns…
The article doesn't properly explain how DRAM is different from SRAM. DRAM has to constantly refresh itself in order not to 'forget' its contents.
Because of that, the act of reading the bit's value means that the data is destroyed. Therefore one of the jobs of the sense amplifier circuit - which converts the tiny voltage from the bit cell to the external voltage - is to recharge the bit.
But that stray capacitance is so small that it naturally discharges through the high, but not infinite, resistance when the transistor is 'off'. Hence, you have to refresh DRAM, by regularly reading every bit frequently enough that it hasn't discharged before you got to it. Usually you might only need to read every row frequently enough, because there's actually a sense amplifier for each column, reading all the bit values in that row, with the column address strobe just selecting which column bit gets output.