Live data from Hacker News

The Pentium as a Navajo Weaving

righto.com

31–40 of 90 posts

Re: The Pentium as a Navajo Weaving

#31
I'm building a stained glass window for our front entrance, as a sometimes chip designer it's going to be a half adder (so much much smaller than a pentium) - the big challenge is showing all the layers (si, implantation, poly, metal, vias etc) I'm only doing 1 level of metal. The result is going to be more of a thin layered sculpture than a traditional stained glass window

Re: The Pentium as a Navajo Weaving

#33
post #31

I'm building a stained glass window for our front entrance, as a sometimes chip designer it's going to be a half adder (so much much smaller than a pentium) - the big challenge is showing all the layers (si, implantation, poly, metal, vias etc) I'm only doing 1 level of metal. The result is going to be more of a thin layered sculpture than a traditional stained glass window

Neat. 2 RTL gates -> 16 CMOS transistors (10 for XOR and 6 for OR)

Re: The Pentium as a Navajo Weaving

#36
post #23
post #2

Author here for your obscure Pentium questions...

I had a dual Pentium II board (made by Tyan, with an Adaptec Raid Option slot) but I don't recall ever seeing a dual P54C board. Did a mainstream motherboard maker ever release one, to your knowledge?

there was tyan, supermicro, and MSI? at least

i thin my board with the dual pentium 60mhz chips was msi.

Re: The Pentium as a Navajo Weaving

#37
post #31

I'm building a stained glass window for our front entrance, as a sometimes chip designer it's going to be a half adder (so much much smaller than a pentium) - the big challenge is showing all the layers (si, implantation, poly, metal, vias etc) I'm only doing 1 level of metal. The result is going to be more of a thin layered sculpture than a traditional stained glass window

Don't bother with the rectilinear pakeha layouts, do your half adders in curvilinear patterns, Koru style

Re: The Pentium as a Navajo Weaving

#38
post #31

I'm building a stained glass window for our front entrance, as a sometimes chip designer it's going to be a half adder (so much much smaller than a pentium) - the big challenge is showing all the layers (si, implantation, poly, metal, vias etc) I'm only doing 1 level of metal. The result is going to be more of a thin layered sculpture than a traditional stained glass window

Neat. 2 RTL gates -> 16 CMOS transistors (10 for XOR and 6 for OR)

Actually I misspoke, it's a full adder and very similar to the one on page 5 here

https://www.cerc.utexas.edu/~jaa/vlsi/lectures/8-1.pdf

Re: The Pentium as a Navajo Weaving

#39
post #31

I'm building a stained glass window for our front entrance, as a sometimes chip designer it's going to be a half adder (so much much smaller than a pentium) - the big challenge is showing all the layers (si, implantation, poly, metal, vias etc) I'm only doing 1 level of metal. The result is going to be more of a thin layered sculpture than a traditional stained glass window

Don't bother with the rectilinear pakeha layouts, do your half adders in curvilinear patterns, Koru style

I am pakeha and tangata triti .... now I have an idea for the next window (I was thinking about a neuron ...)
Post reply on HN