Earlier quoted context omitted.
I think they are saying it from the perspective rather than two separate banks which are rarely both full it's one bank which is only ever full when 100% of the hardware is full. That said I think many miss that's how integrated graphics memory management had been working on x86 systems for many many years already. I.e. the "dedicated RAM" slider in the boot firmware is a legacy holdover that should be set to a minim…
They are saying it from the perspective of the RAM being on the same die as the CPU. This is one of the innovations of the Apple Silicon architecture as it SIGNIFICANTLY reduces memory access latency. It's not just TSMC's 3nm process. It's also Apple engineering.
This engineering was common in x86 CPUs by 2013 when AMD introduced Heterogeneous System Architecture which utilized Heterogeneous Uniform Memory Access. The approach has its upsides and downsides, the latter generally being a unified bus tends to have much lower overall bandwidth (even in the Max) and runtime scalability issues. Upsides are more obvious for the types of systems people want APUs for in the first place though so that's usually fine.
The main bit of engineering Apple should be lauded for in the memory department is the gumption to throw the hundreds of GB/s at the mid and high end models.