Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
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Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#2Incredible result! This is a tremendous amount of work and does seem like RV is at its limits in some of these cases. The bit gather and scatter instructions should become an extension!
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#3I hope they're able to get this ISA-level feedback to people at RVI
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#4I hope they're able to get this ISA-level feedback to people at RVI
None of this is new. None of it.
In fact, bitfield extract is such an obvious oversight that it is my favourite example of how idiotic the RISCV ISA is (#2 is lack of sane addressing modes).
Some of the better RISCV designs, in fact, implement a custom instr to do this, eg: BEXTM in Hazard3: https://github.com/Wren6991/Hazard3/blob/stable/doc/hazard3....
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#5Article is a bit short on "the basics" - I assumed they used some kind of wine port to run it. But it seems they implemented the x86_64 ISA on a RISC-V chip in some way - anyone can shed more light on that part how that is done?
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#6Article is a bit short on "the basics" - I assumed they used some kind of wine port to run it. But it seems they implemented the x86_64 ISA on a RISC-V chip in some way - anyone can shed more light on that part how that is done?
The basics are here: https://box86.org/ It is an emulator but:
> Because box86 uses the native versions of some “system” libraries, like libc, libm, SDL, and OpenGL, it’s easy to integrate and use with most applications, and performance can be surprisingly high in some cases.
Wine can also be compiled/run as native.
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#7I hope they're able to get this ISA-level feedback to people at RVI
The scalar efficiency SIG has already been discussing bitfield insert and extract instructions.
We figured out yesterday [1], that the example in the article can already be done in four risc-v instructions, it's just a bit trickier to come up with it:
# a0 = rax, a1 = rbx
slli t0, a1, 64-8
rori a0, a0, 16
add a0, a0, t0
rori a0, a0, 64-16
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#8I hope they're able to get this ISA-level feedback to people at RVI
None of this is new. None of it. In fact, bitfield extract is such an obvious oversight that it is my favourite example of how idiotic the RISCV ISA is (#2 is lack of sane addressing modes). Some of the better RISCV designs, in fact, implement a custom instr to do this, eg: BEXTM in Hazard3: https://github.com/Wren6991/Hazard3/blob/stable/doc/hazard3....
Whoa, someone else who doesn't believe that the RISC-V ISA is 'perfect'!
I'm curious: how the discussions on the bitfield extract have been going? Because it does really seem like an obvious oversight and something to add as a 'standard extension'.
What's your take on
1) unaligned 32bit instructions with the C extension?
2) lack of 'trap on overflow' for arithmetic instructions? MIPS had it..
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#9That screenshot shows 31 gb of ram which is distinctly more than the mentioned dev board at max specs. Are they using something else here?
Re: Box64 and RISC-V in 2024: What It Takes to Run the Witcher 3 on RISC-V
#10That screenshot shows 31 gb of ram which is distinctly more than the mentioned dev board at max specs. Are they using something else here?