Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

Ask HN: Weirdest Computer Architecture?

news.ycombinator.com

Post reply on HN
Print view View original

101–109 of 109 posts

Re: Ask HN: Weirdest Computer Architecture?

#101

Post by convivialdingo »

AstroJetson wrote: post #82

Huge fan of the Burroughs Large Systems Stack Machines. https://en.wikipedia.org/wiki/Burroughs_Large_Systems They had an attached scientific processor to do vector and array computations. https://bitsavers.org/pdf/burroughs/BSP/BSP_Overview.pdf

Incredibly odd system which had no assembler. Almost a pure stack machine, some models had a 51 bit word (48 bit and a 3 bit tag). One of the first machines with NUMA & SMP, segmented memory, and virtual memory (but with all the oddness of a first innovator).

I knew some of the engineers at Unisys who were still supporting Clearpath and Libra. Even they thought Burroughs was weird...

Re: Ask HN: Weirdest Computer Architecture?

#102

Post by em-bee »

Bluestein wrote: post #100
em-bee wrote: post #74

Earlier quoted context omitted.

i did get a sony picturebook with a transmeta processor. the problem was that as a consumer i didn't notice anything special about it. for transmeta to make it they would have had to either be cheaper or faster or use less power to be attractive for consumer devices.

I seem to recall them machines not being cheaper, which was my main hope at the time :)

i got mine as a gift, so i don't remember the price, but i don't think it was cheap. however that would not even bother me. they would have at least had to be cheaper for manufacturers to make it worth it to put them into more devices.

Re: Ask HN: Weirdest Computer Architecture?

#103

Post by AstroJetson »

convivialdingo wrote: post #101
AstroJetson wrote: post #82

Huge fan of the Burroughs Large Systems Stack Machines. https://en.wikipedia.org/wiki/Burroughs_Large_Systems They had an attached scientific processor to do vector and array computations. https://bitsavers.org/pdf/burroughs/BSP/BSP_Overview.pdf

Incredibly odd system which had no assembler. Almost a pure stack machine, some models had a 51 bit word (48 bit and a 3 bit tag). One of the first machines with NUMA & SMP, segmented memory, and virtual memory (but with all the oddness of a first innovator). I knew some of the engineers at Unisys who were still supporting Clearpath and Libra. Even they thought Burroughs was weird...

Assembler was possible in both ESPOL and NEWP, there was a way to load the initial stack at boot time to get things in place. But it was only a few instructions worth. There was actually a patch to the Algol compiler from UC Davis that let you put any instruction in place. I used that to create named pipes for applications to use.

There was interesting procedure names in the Master Control Program (yes, Tron fans, the real MCP) JEDGARHOOVER was central to system level security. I taught the customer facing MCP class for a few years.

In the early days they gave you the source code and it wasn't uncommon for people to make patches and share them around. Everyone sent patches into the plant and in a release or two you would see them come back as official code.

Re: Ask HN: Weirdest Computer Architecture?

#105

Post by patterner »

nrr wrote: post #25
runjake wrote: post #4

Here are some architectures that might interest you. Note these are links that lead to rabbit holes. 1. Transmeta: https://en.wikipedia.org/wiki/Transmeta 2. Cell processor: https://en.wikipedia.org/wiki/Cell_(processor) 3. VAX: https://en.wikipedia.org/wiki/VAX (Was unusual for it's time, but many concepts have since been adopted) 4. IBM zArchitecture: https://en.wikipedia.org/wiki/Z/Architecture (This stuff is comp…

For those really wanting to dig into z/Architecture: https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-78... > The Wikipedia link has it as its first reference, but it's honestly worth linking directly here. I highly recommend trying to get someone to give you a TSO/E account and picking up HLASM.

i loved working with z/Arch assembly. best job i ever had.

Re: Ask HN: Weirdest Computer Architecture?

#106

Post by LargoLasskhyfv »

mikewarot wrote: post #13
bjconlan wrote: post #11

Earlier quoted context omitted.

On reading this I thought "oh someone's doing the Green Arrays thing" but this looks like it pre-dates those CPUs by some time. But as nobody has mentioned it yet surprisingly: https://www.greenarraychips.com/ albeit perhaps not weird; just different

The Green arrays chips are quite interesting in their own right. The ability to have a grid of CPUs each working at part of a problem could be used in parallelizing a lot of things, including the execution of LLMs. There are secondary consequences of breaking computation down to a directed acyclic graph of binary logic operations. You can guarantee runtime, as you know a-priori how long each step will take. Splitting…

Nag nag...(meant inspirational in case you're unaware of it)...

Regarding Amdahl's law and avoiding its complications this fits:

https://duckduckgo.com/?q=Apple-CORE+D-RISC+SVP+Microgrids+U...

(Not limited to SPARC, conceptually it's applicable almost anywhere else)

From the software-/programming-/compiler-side this fits right on top it:

https://duckduckgo.com/?q=Dybvig+Nanopass

(Also conceptually, doesn't have to be Scheme, but why not? It's nice.)

Re: Ask HN: Weirdest Computer Architecture?

#107

Post by yencabulator »

elkekeer wrote: post #49

A multi-core Propeller processor by Parallax ( https://en.wikipedia.org/wiki/Parallax_Propeller ) in which multitasking is done by cores (called cogs) taking turns: first, code is executed on the first cog, then, after a while, on the second, then on the third, etc.

Linked in another comment, that seems to be an example of https://en.m.wikipedia.org/wiki/Barrel_processor

Re: Ask HN: Weirdest Computer Architecture?

#108

Post by yencabulator »

Just the operating system, but I like Barrelfish's idea of having a separate kernel on every core and doing message passing. Each "CPU driver" is single-threaded, non-preemptible (no interrupts), shares no state, bounded-time, and runs to completion. Userspace programs can access shared memory, but the low-level stuff doesn't do that. Bounded-time run to completion kinda makes me think of seL4, if it was designed to be natively multicore.

https://en.wikipedia.org/wiki/Barrelfish_(operating_system)

https://barrelfish.org/publications/TN-000-Overview.pdf

Post reply on HN