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Memory Mapping an FPGA from an STM32

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Re: Memory Mapping an FPGA from an STM32

#41

Post by buescher »

rvense wrote: post #38
buescher wrote: post #13

Earlier quoted context omitted.

I keep running into that also. It's like the common mental model of a microcontroller froze around Y2K as a sort of headless VIC-20. I had an FAE , and a good one, from a major supplier tell me "you can't implement a filter" on a low-end micro that was roughly as powerful as an early nineties DSP.

Cortex-Ms, man. A lot of 'em you just give 3.3V and a couple of bypass caps, and GCC will use the single-cycle hardware MAC (for M4 and above) if you just write the straight-forward C code and you can put it on there in 600ms with DFU. I'm a hobbyist, not an embedded wizard, but it really seems *pretty* good compared to what I understand about the old days. (Like I like retro stuff and during COVID I bought an old DS…

They're amazing. And - you can run a PC emulator on an ESP32. Sure, you need the fancy ram. OK. And then people will tell me an ESP32 can't do things that people definitely were doing on bare-bones PCs in the eighties.

Re: Memory Mapping an FPGA from an STM32

#42

Post by azonenberg »

dmitrygr wrote: post #37
azonenberg wrote: post #20

Earlier quoted context omitted.

I have encountered issues with QSPI (mostly caused by the annoying prefetch queue) which is why I am switching to the FMC for FPGA interfacing (i.e. not using OCTOSPI). That was the whole point of this experiment, validating FMC as a replacement for my legacy OCTOSPI based MCU-APB bridge. I have a previous board using QSPI reliably in indirect mode (i.e. not memory mapped) but found it was full of pain when memory ma…

> 100K reads/writes of a 32-bit register You'll hit almost no bugs if you keep accessing the same address in a loop. Lucky you :)

Yeah but again, we're talking about the FMC here not the OCTOSPI.

Have you hit issues with the FMC? From what other people are telling me, the OCTOSPI is full of land mines and the FMC is pretty decent. The worst errata I've encountered so far is two dummy clocks with CS# asserted at the end of a read burst.

Re: Memory Mapping an FPGA from an STM32

#43

Post by syntheticgate »

azonenberg wrote: post #42
dmitrygr wrote: post #37

Earlier quoted context omitted.

> 100K reads/writes of a 32-bit register You'll hit almost no bugs if you keep accessing the same address in a loop. Lucky you :)

Yeah but again, we're talking about the FMC here not the OCTOSPI. Have you hit issues with the FMC? From what other people are telling me, the OCTOSPI is full of land mines and the FMC is pretty decent. The worst errata I've encountered so far is two dummy clocks with CS# asserted at the end of a read burst.

lol, I'm working on an FMC-FPGA interface at work right now and discovered this same chipselect behavior.

Re: Memory Mapping an FPGA from an STM32

#44

Post by azonenberg »

syntheticgate wrote: post #43
azonenberg wrote: post #42

Earlier quoted context omitted.

Yeah but again, we're talking about the FMC here not the OCTOSPI. Have you hit issues with the FMC? From what other people are telling me, the OCTOSPI is full of land mines and the FMC is pretty decent. The worst errata I've encountered so far is two dummy clocks with CS# asserted at the end of a read burst.

lol, I'm working on an FMC-FPGA interface at work right now and discovered this same chipselect behavior.

It's a documented errata, 2.6.1 on page 8 of ES0491.

Re: Memory Mapping an FPGA from an STM32

#45

Post by anitil »

mystified5016 wrote: post #25
dmitrygr wrote: post #19

Be veeeery careful. STM32H QSPI peripheral is FULL OF very nasty bugs, especially the second version (supports writes) that you find in STM32H0B chips . You are currently avoiding them by having QSPI mapped as device memory, but the minute you attempt to use it with cache or run code from it, or (god help you) put your stack, heap, and/or vector table on a QSPI device, you are in for a world of poorly-debuggable 1:1,…

What the hell is going on at ST? Every STM uC I've tried to use in the past few years has had showstopper bugs with loads of very similar complaints online dating back to the release of the part. Bugs that have been in the wild for years and still exist in the current production run. After burning enough company time chasing bugs through ST's crappy silicon, I've had to just swear them off entirely. We're an Atmel ho…

It seems endemic with embedded devices. Only big customers get the true list of errata, and of course the errata are random PDFs rather than a useful format. Even just having them on an ftp site with all the errata in one spot would save so much pain!

Re: Memory Mapping an FPGA from an STM32

#46

Post by kevin_thibedeau »

anitil wrote: post #45
mystified5016 wrote: post #25

Earlier quoted context omitted.

What the hell is going on at ST? Every STM uC I've tried to use in the past few years has had showstopper bugs with loads of very similar complaints online dating back to the release of the part. Bugs that have been in the wild for years and still exist in the current production run. After burning enough company time chasing bugs through ST's crappy silicon, I've had to just swear them off entirely. We're an Atmel ho…

It seems endemic with embedded devices. Only big customers get the true list of errata, and of course the errata are random PDFs rather than a useful format. Even just having them on an ftp site with all the errata in one spot would save so much pain!

Sometimes you don't even get a PDF. Their Ethernet drivers for Cortex-M7 have been broken for years with subtle cache coherency bugs and the only discussion of it is a forum thread with now obsolete example code.

Re: Memory Mapping an FPGA from an STM32

#47

Post by anyfoo »

azonenberg wrote: post #32
15155 wrote: post #27

Earlier quoted context omitted.

Zynq 7010s are $2.50 and are a hell of a lot more chip than an RP2040. If you already have the design (or copy one of the 50 available), it's a good option when you don't want to fight the chip. PIO has extraordinarily sloppy timing (skew in all categories) compared to the cheapest and smallest FPGAs.

Where are you getting them for $2.50?? The XC7Z010-1CLG225C is $74.83 at Digikey in qty 1. Checking sketchier places Win-Source has the CLG400 package for $22.20 and even the cheapest aliexpress seller wants $4.84 for something marked as a 7Z010 that may or may not be legit. Also "fight the chip" is pretty much the definition of what I did last time I did a zynq project. Just give me a plain FPGA and MCU with no wiza…

What parts do you have to fight? I’ve been using Zynqs for about almost a decade or so, and I really enjoy them. But that’s for personal projects with a lot of freedom, so I’m curious what problems arise in more commercial/professional settings.

Nowadays, I only often wish I had their ARMv8 chips instead of the old ARMv7 32bit architecture because that’s just showing its age, but that’s par for the course of using ARMv7, and doesn’t affect the PL side (much, except for interfacing sometimes).

Re: Memory Mapping an FPGA from an STM32

#48

Post by anyfoo »

15155 wrote: post #33
azonenberg wrote: post #32

Earlier quoted context omitted.

Where are you getting them for $2.50?? The XC7Z010-1CLG225C is $74.83 at Digikey in qty 1. Checking sketchier places Win-Source has the CLG400 package for $22.20 and even the cheapest aliexpress seller wants $4.84 for something marked as a 7Z010 that may or may not be legit. Also "fight the chip" is pretty much the definition of what I did last time I did a zynq project. Just give me a plain FPGA and MCU with no wiza…

https://www.aliexpress.us/item/3256803970893483.html I've ordered trays (and they send the OEM tray) - unique barcodes, legit. > Just give me a plain FPGA and MCU with no wizards or GUIs or automatic code generation. You can pretty much cut out all of their tools and get a pure Yocto/Vivado TCL build for the bitstream for the 7 series Zynqs. Very low touch. Their IO planner (in the Vivado IP integrator) is somewhat n…

I don’t even find Vivado that bad, but maybe I have Stockholm syndrome. Or maybe it’s because I’m forced to use Intel Quartus right now and wish it was Vivado every time.

Re: Memory Mapping an FPGA from an STM32

#49

Post by scottapotamas »

15155 wrote: post #33
azonenberg wrote: post #32

Earlier quoted context omitted.

Where are you getting them for $2.50?? The XC7Z010-1CLG225C is $74.83 at Digikey in qty 1. Checking sketchier places Win-Source has the CLG400 package for $22.20 and even the cheapest aliexpress seller wants $4.84 for something marked as a 7Z010 that may or may not be legit. Also "fight the chip" is pretty much the definition of what I did last time I did a zynq project. Just give me a plain FPGA and MCU with no wiza…

https://www.aliexpress.us/item/3256803970893483.html I've ordered trays (and they send the OEM tray) - unique barcodes, legit. > Just give me a plain FPGA and MCU with no wizards or GUIs or automatic code generation. You can pretty much cut out all of their tools and get a pure Yocto/Vivado TCL build for the bitstream for the 7 series Zynqs. Very low touch. Their IO planner (in the Vivado IP integrator) is somewhat n…

I was interested to see, or at least what state they're in so I grabbed a couple. Might try to compare them against some genuine ones with CT and destructive inspection.

On the chance they're half reasonable, thanks for the link.

Re: Memory Mapping an FPGA from an STM32

#50

Post by 15155 »

scottapotamas wrote: post #49
15155 wrote: post #33

Earlier quoted context omitted.

https://www.aliexpress.us/item/3256803970893483.html I've ordered trays (and they send the OEM tray) - unique barcodes, legit. > Just give me a plain FPGA and MCU with no wizards or GUIs or automatic code generation. You can pretty much cut out all of their tools and get a pure Yocto/Vivado TCL build for the bitstream for the 7 series Zynqs. Very low touch. Their IO planner (in the Vivado IP integrator) is somewhat n…

I was interested to see, or at least what state they're in so I grabbed a couple. Might try to compare them against some genuine ones with CT and destructive inspection. On the chance they're half reasonable, thanks for the link.

Let me know if the barcodes are anything but unique/perfect. This has been the case with many vendors, but these chips are cheap enough that you can try 50 vendors.
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