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TSMC unveils 1.6nm process technology with backside power delivery

tomshardware.com

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Re: TSMC unveils 1.6nm process technology with backside power delivery

#51

Sounds like a response to Intel's 18A process [0], which is also coming in 2026. [0] https://www.tomshardware.com/tech-industry/manufacturing/int...

This is a response to something that’s coming in 2 years? Incredible how far ahead they are

Fabs have a 3+ year lead time from prototyping the node to having it produce production wafers.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#52
post #35
post #2

could someone ELi5 the backside power delivery please ?

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

Thanks this was a very useful summary for me!

Re: TSMC unveils 1.6nm process technology with backside power delivery

#53
post #46
post #40

Earlier quoted context omitted.

1.6 nm is 16 A. If they continue the BS for much longer, the "feature size" will be smaller than the lattice of Si.

You're the one calling it a feature size, not TSMC.

I’m sure you agree that the measurement given is a marketing term and is generally unhelpful beyond ‘it’s smaller than the current number’.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#54
post #18

Earlier quoted context omitted.

Because it's not measuring anything, except the tech generation. It conveys about as much information as "iPhone 14".

It's at least more easily understandable (lower is newer) than the average tech product naming scheme, especially those by Microsoft.

[deleted]

Re: TSMC unveils 1.6nm process technology with backside power delivery

#55

Earlier quoted context omitted.

Number represents transistor density. 2nm has ~twice the density of 4nm. If you ignore nm as unit of distance it makes sense.

They're using the wrong units if we need to consider the nanometer as something other than a measure of distance.

In some applications it helps to be fluid in exchanging distance as time with time as distance.

http://dataphys.org/list/grace-hopper-nanoseconds/

and the field of play here isn't 1D linear .. it's somewhere sort of a bit slightly > 2D (elements can be stacked, there are limitations on how much and how close)

Re: TSMC unveils 1.6nm process technology with backside power delivery

#56
post #35
post #2

could someone ELi5 the backside power delivery please ?

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

thank you for the explanation! It really helped

Re: TSMC unveils 1.6nm process technology with backside power delivery

#57
post #50

A16 in 2027 vs Intel's 18A in full swing by 2026 feels like a miss on TMSCs behalf. This looks like an open door for fabless companies to try Intel's foundry service.

Intel has made lots of big promises, they have yet to catch us to TSMC

Re: TSMC unveils 1.6nm process technology with backside power delivery

#58
post #49
post #35

Earlier quoted context omitted.

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

[flagged]

> I detest ELI5 as it's managerial nonsense.

I thought it came from Reddit, which is about as far from ‘managerial’ as one can get.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#59
Comments about the marketing driven nm measurements aside, this still looks like another solid advance for TSMC. They are already significantly ahead of Samsung and Intel on transistor density. TSMC is at 197 MTr/mm2 wile Samsung is at 150 MTr/mm2 and Intel is at 123 MTr/mm2. This 1.6nm process will put them around 230 MTr/mm2 by 2026. When viewed by this metric, Intel is really falling behind.

Re: TSMC unveils 1.6nm process technology with backside power delivery

#60
post #35
post #2

could someone ELi5 the backside power delivery please ?

ELI5: ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power: * Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better. * Big wires, if near signal wires, can interfere with them working optima…

> You need very tiny wires through very tiny holes in locations very precisely aligned on both sides. Aligning things on the scale of nanometers is very, very hard.

Do you need to align that precisely? Can't the power side have very large landing pads for the wires from the signal side to make it much easier?

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