>1.6nm Gotta love how we now have fractions of a near meaningless metric.
Wonder how long until its back to round numbers? - 800pm
TSMC unveils 1.6nm process technology with backside power delivery
31–40 of 209 posts
Re: TSMC unveils 1.6nm process technology with backside power delivery
#32> This technology is tailored specifically for AI and HPC processors that tend to have both complex signal wiring and dense power delivery networks Uh?
Pardon?
Re: TSMC unveils 1.6nm process technology with backside power delivery
#33Re: TSMC unveils 1.6nm process technology with backside power delivery
#34Earlier quoted context omitted.
https://www.imec-int.com/en/articles/how-power-chips-backsid... has some explanation that's a bit beyond ELI5, but they have 2 pictures: frontside: https://www.imec-int.com/_next/image?url=%2Fsites%2Fdefault%... backside: https://www.imec-int.com/_next/image?url=%2Fsites%2Fdefault%... Another graphic samsung used: https://www.thelec.net/news/photo/202210/4238_4577_1152.jpg From https://www.tomshardware.com/pc-compone…
the pics go to 404
thanks, I've fixed them
btw, you appear to be shadow banned, probably on account of being downvoted for making short comments like "good" or "I don't get it"
Short & simple responses may be adequate at times, but usually people will view it as not adding anything
Perhaps reviewing guidelines https://news.ycombinator.com/newsguidelines.html will give an idea of the ideal being yearned for (granted, it's an ideal). In general, trying to enhance the conversation with relevant information/ideas. "your links are 404" was definitely relevant here
Re: TSMC unveils 1.6nm process technology with backside power delivery
#35could someone ELi5 the backside power delivery please ?
ELI5:
ICs are manufactured on silicon disks called wafers. Discs have two sides, and traditionally, everything was done on top. We can now do power on the bottom. This makes things go faster and use less power:
* Power wires are big (and can be a bit crude). The bigger the better. Signal wires are small and precise. Smaller is generally better.
* Big wires, if near signal wires, can interfere with them working optimally (called "capacitance").
* Capacitance can slow down signals on the fine signal wires.
* Capacitance also increases power usage when ones become zeros and vice-versa on signal wires.
* Big wires also take up a lot of space.
* Putting them on the back of the wafer means that things can go faster and use less power, since you don't have big power wires near your fine signal wires.
* Putting them in back leaves a lot more space for things in front.
* Capacitance between power wires (which don't carry signal) actually helps deliver cleaner power too, which is a free bonus!
This is hard to do, since it means somehow routing power through the wafer. That's why we didn't do this before. You need very tiny wires through very tiny holes in locations very precisely aligned on both sides. Aligning things on the scale of nanometers is very, very hard.
How did I do?
Re: TSMC unveils 1.6nm process technology with backside power delivery
#36> This technology is tailored specifically for AI and HPC processors that tend to have both complex signal wiring and dense power delivery networks Uh?
There are certain trade offs when designing process. TSMC researched with partners how AI and HPC (high performance computing) chips most likely will look like and adjusted process accordingly.
In fact this is big deal as until recently the processes were more tailored toward mobile application (that is were trading some switching performance for lower power consumption). Look like we are back in 2000s when speed/density is again more important than power consumption.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#37could someone ELi5 the backside power delivery please ?
Half your wires deliver power, half deliver signal. So if you do both on the same side, you need twice the density of wires. If you split the delivery into two parts, you get double the density without needing to make things smaller.
This isn't quite right. Big wires (ideally entire planes) deliver power. Small wires deliver signal. Half and half isn't the right split, and you don't want to make power wires smaller.
The very different requirements of the two is where a lot of the gains come in.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#38>1.6nm Gotta love how we now have fractions of a near meaningless metric.
TSMC N5 is indeed about 30% more Transistors/mm2 than N7 as you might expect so seems reasonably meaningful?
Re: TSMC unveils 1.6nm process technology with backside power delivery
#39Re: TSMC unveils 1.6nm process technology with backside power delivery
#40>1.6nm Gotta love how we now have fractions of a near meaningless metric.
TSMC N5 is indeed about 30% more Transistors/mm2 than N7 as you might expect so seems reasonably meaningful?
1.6 nm is 16 A. If they continue the BS for much longer, the "feature size" will be smaller than the lattice of Si.