TSMC unveils 1.6nm process technology with backside power delivery
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Re: TSMC unveils 1.6nm process technology with backside power delivery
#2could someone ELi5 the backside power delivery please ?
Re: TSMC unveils 1.6nm process technology with backside power delivery
#3could someone ELi5 the backside power delivery please ?
Signal wires and power wires are not routed together, but separately.
As a result, transistors are sandwiched between two wiring stacks. Resulting in lower noise, but makes heat removal a bit harder AFAICS.
See the image at: https://www.custompc.com/wp-content/sites/custompc/2023/06/I...
Re: TSMC unveils 1.6nm process technology with backside power delivery
#4It seems the actually impressive thing here is the 15-20% less power consumption at same n2 complexity/speed.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#5could someone ELi5 the backside power delivery please ?
An article on the topic though about Intel:
Re: TSMC unveils 1.6nm process technology with backside power delivery
#6Sounds like a response to Intel's 18A process [0], which is also coming in 2026.
[0] https://www.tomshardware.com/tech-industry/manufacturing/int...
Re: TSMC unveils 1.6nm process technology with backside power delivery
#7could someone ELi5 the backside power delivery please ?
instead of signals and power path going through the same side (frontside) causing all sorts of issues and inefficiency, they're decoupling where power is coming from (from the other, backside, err side).
More importantly, intel saw it as one of two key technologies of them moving into angstrom era, and was touting itself they'll be the first one to bring it to life (not sure they did).. so this seems to be more of a business power move.
more on all of it from anandtech: https://www.anandtech.com/show/18894/intel-details-powervia-...
Re: TSMC unveils 1.6nm process technology with backside power delivery
#8>1.6nm
Gotta love how we now have fractions of a near meaningless metric.
Re: TSMC unveils 1.6nm process technology with backside power delivery
#9could someone ELi5 the backside power delivery please ?
I'm also clueless. First search brings up https://www.tomshardware.com/news/intel-details-powervia-bac... with a nice diagram
It looks like the topology for backside moves the transistors to the middle so "singal wires and power wires are decoupled and optimized separately" instead of "compete[ing] for the same resources at every metal layer"
Re: TSMC unveils 1.6nm process technology with backside power delivery
#10could someone ELi5 the backside power delivery please ?
https://www.imec-int.com/en/articles/how-power-chips-backsid... has some explanation that's a bit beyond ELI5, but they have 2 pictures:
frontside: https://www.imec-int.com/_next/image?url=%2Fsites%2Fdefault%...
backside: https://www.imec-int.com/_next/image?url=%2Fsites%2Fdefault%...
Another graphic samsung used: https://www.thelec.net/news/photo/202210/4238_4577_1152.jpg
From https://www.tomshardware.com/pc-components/cpus/samsung-to-i...
> Typically, backside power delivery enables thicker, lower-resistance wires, which can deliver more power to enable higher performance and save power. Samsung's paper noted a 9.2% reduction in wiring length, enhancing performance