171–180 of 184 posts
https://stefan.t8k2.com/rh/PRAC/index.html Chapter 16: "DDR5 Per Row Activation Counting (PRAC)". PRAC introduces two key mechanisms for comprehensive Rowhammer defenses: an Activation Counter for every DRAM row and a mechanism that triggers when an Activation Counter reaches a specific threshold. This allows the DRAM to pause the memory controller from issuing new commands, giving it time to refresh potential victim…
Earlier quoted context omitted.
I wish we could mix 'I don't care about side channels, use them all' with 'I'm paranoid about side channels, plug them all' on the same machine. Disable speculative execution on one core, no frequency adjustment, no prefetching, sr-io/pcie-bypass some devices... E-cores but for the side-channel-paranoid (in a good way).
Bring back EIEIO, like on Old Macs, but perhaps with a slightly expanded definition of what constitutes I/O: Enforce In-order Execution of I/O (EIEIO) is an assembly language instruction used on the PowerPC central processing unit (CPU) which prevents one memory or input/output (I/O) operation from starting until the previous memory or I/O operation completed. This instruction is needed ] as I/O controllers on the sy…
This is what we should reserve Nobel prizes in computer science for
Earlier quoted context omitted.
Bring back EIEIO, like on Old Macs, but perhaps with a slightly expanded definition of what constitutes I/O: Enforce In-order Execution of I/O (EIEIO) is an assembly language instruction used on the PowerPC central processing unit (CPU) which prevents one memory or input/output (I/O) operation from starting until the previous memory or I/O operation completed. This instruction is needed ] as I/O controllers on the sy…
> EIEIO, like on Old Macs This is what we should reserve Nobel prizes in computer science for
https://stefan.t8k2.com/rh/PRAC/index.html Chapter 16: "DDR5 Per Row Activation Counting (PRAC)". PRAC introduces two key mechanisms for comprehensive Rowhammer defenses: an Activation Counter for every DRAM row and a mechanism that triggers when an Activation Counter reaches a specific threshold. This allows the DRAM to pause the memory controller from issuing new commands, giving it time to refresh potential victim…
I'll bet good money that this gets turned into a timing attack soon - it's a prototypical address-dependent delay.
Earlier quoted context omitted.
I wish we could mix 'I don't care about side channels, use them all' with 'I'm paranoid about side channels, plug them all' on the same machine. Disable speculative execution on one core, no frequency adjustment, no prefetching, sr-io/pcie-bypass some devices... E-cores but for the side-channel-paranoid (in a good way).
Host cores and guest cores.
Earlier quoted context omitted.
It's never going to happen because Dell counts every penny.
JEDEC could only standardize ECC modules. Microsoft, Intel or AMD can, anytime, require ECC for their certification/logo programs. Intel and AMD could even make their new chips only boot with ECC. And FCC could make ECC a requirement for certification. All these parties (and more) are enabling non-ECC memory, to the detriment of mankind.
https://stefan.t8k2.com/rh/PRAC/index.html Chapter 16: "DDR5 Per Row Activation Counting (PRAC)". PRAC introduces two key mechanisms for comprehensive Rowhammer defenses: an Activation Counter for every DRAM row and a mechanism that triggers when an Activation Counter reaches a specific threshold. This allows the DRAM to pause the memory controller from issuing new commands, giving it time to refresh potential victim…
I'll bet good money that this gets turned into a timing attack soon - it's a prototypical address-dependent delay.
Earlier quoted context omitted.
Just to make sure I understand: you're saying that checking L1/L2/L3 takes around 35ns, and then the CPU accesses DRAM which takes 10ns? If that's so, how is L3 cache any faster than DRAM? Also, can you explain why the memory controller adds some latency?
An L3 hit only takes ~15 ns so that means another 15-20 ns is spent traversing the fabric and memory controller. I'm not sure what all is involved there but for Intel it has to go around the ring and for AMD it has to cross chiplets.
Earlier quoted context omitted.
An L3 hit only takes ~15 ns so that means another 15-20 ns is spent traversing the fabric and memory controller. I'm not sure what all is involved there but for Intel it has to go around the ring and for AMD it has to cross chiplets.
Interesting. If an L3 hit takes 15 ns, then based on your argument a hypothetical CPU with only one core (and hence no fabric) would be better off without L3, since a DRAM read can be performed in just 10 ns.
Earlier quoted context omitted.
An L3 hit only takes ~15 ns so that means another 15-20 ns is spent traversing the fabric and memory controller. I'm not sure what all is involved there but for Intel it has to go around the ring and for AMD it has to cross chiplets.
Interesting. If an L3 hit takes 15 ns, then based on your argument a hypothetical CPU with only one core (and hence no fabric) would be better off without L3, since a DRAM read can be performed in just 10 ns.