JEDEC Extends DDR5 Memory Spec to 8800 MT/S, Adds Anti-Rowhammer Features • Hacker News Board

Re: JEDEC Extends DDR5 Memory Spec to 8800 MT/S, Adds Anti-Rowhammer Features

#21

Post by smallmancontrov » Mon, Apr 22, 2024, 7:36 PM UTC

touisteur wrote: post #19

pshirshov wrote: post #11

Earlier quoted context omitted.

And potentially opens a whole new family of side channels.

I wish we could mix 'I don't care about side channels, use them all' with 'I'm paranoid about side channels, plug them all' on the same machine. Disable speculative execution on one core, no frequency adjustment, no prefetching, sr-io/pcie-bypass some devices... E-cores but for the side-channel-paranoid (in a good way).

Bring back EIEIO, like on Old Macs, but perhaps with a slightly expanded definition of what constitutes I/O:

    Enforce In-order Execution of I/O (EIEIO) is an assembly language
    instruction used on the PowerPC central processing unit (CPU) which
    prevents one memory or input/output (I/O) operation from starting until
    the previous memory or I/O operation completed. This instruction is needed ]
    as I/O controllers on the system bus require that accesses follow a
    particular order, while the CPU reorders accesses to optimize memory 
    bandwidth usage.

Re: JEDEC Extends DDR5 Memory Spec to 8800 MT/S, Adds Anti-Rowhammer Features

#22

Post by foota » Mon, Apr 22, 2024, 7:37 PM UTC

mungoman2 wrote: post #18

londons_explore wrote: post #4

I'd like to see the spec tackle latency with a "send then confirm" approach. Ie. The RAM can reply to a read request with data, then a couple of clock cycles later it can confirm (via a flag) that the data it originally sent was correct. This is helpful because it means the timing can be tightened to the typical access times, rather than the worst case access time (eg. the slowest preamp on the highest capacitance me…

How many cycles could this actually save? I would assume the latency to actually get data from DDR is only a small part of the whole round-trip in a L1 miss. Actual savings much smaller than 30%.

Most of the cost of an L3 miss comes after the miss itself, for most architectures I've seen.

E.g., on Skylake an L3 hit is 80 cycles (~20ns) whereas a RAM access is 80 cycles plus 50 nanos (~70 nanos). See https://www.7-cpu.com/cpu/Skylake_X.html