Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
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Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#2Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#3Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#4This was a descendent of the Berkeley RISC, and it had register windows in what might be a more advanced design.
As far as I know, it was used in the AMD K5 x86 CPU as the backend behind an x86 translation layer.
Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#5The interesting thing that I discovered within the last year is that AMD also sold a processor very similar to SPARC, the 29000 (AMD 29k). This was a descendent of the Berkeley RISC, and it had register windows in what might be a more advanced design. As far as I know, it was used in the AMD K5 x86 CPU as the backend behind an x86 translation layer. https://en.wikipedia.org/wiki/AMD_Am29000
Clip of Philip describing AMD 29k: https://youtu.be/I5cYxLg7Vfc
Full Episode: https://microarch.club/episodes/1/
Previous HN Post: https://news.ycombinator.com/item?id=39452960
Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#6The interesting thing that I discovered within the last year is that AMD also sold a processor very similar to SPARC, the 29000 (AMD 29k). This was a descendent of the Berkeley RISC, and it had register windows in what might be a more advanced design. As far as I know, it was used in the AMD K5 x86 CPU as the backend behind an x86 translation layer. https://en.wikipedia.org/wiki/AMD_Am29000
I actually recently interviewed one of the folks (Philip Freidin) who worked on the 29k. Clip of Philip describing AMD 29k: https://youtu.be/I5cYxLg7Vfc Full Episode: https://microarch.club/episodes/1/ Previous HN Post: https://news.ycombinator.com/item?id=39452960
Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#7There was no MMU and the direct mapped data caches were not coherent (data segments had to be padded to a cache line to avoid the processors overwriting each others memory).
The chip was designed by Les Kohn of i860 fame. Here's a pic of an engineering sample with a 2001 date code.
Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#8Btw, someone should really write a spiritual sequel to "Inside the Machine: An Illustrated Introduction to Microprocessors and Computer Architecture"
Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#9Re: Interview with Robert Garner, Lead Designer of SPARC at Sun Microsystems [video]
#10This series/podcast is fantastic. It is worth checking out if you enjoyed Hannibal's old articles on Ars Technica, but don't mind a more human touch to it. Btw, someone should really write a spiritual sequel to "Inside the Machine: An Illustrated Introduction to Microprocessors and Computer Architecture"