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Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

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Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#51

Post by pkkim »

qzcx wrote: post #37

As someone who's also done a lot of DV and DV tools, I love to see it. This gap was something I took away from attending DVCon last year and seeing all the papers from folks reinventing in the same verif tools. Feeling inspired after DVCon, I was sick of how annoying our test infrastructure was to interact with so I built a vscode extension as a front end to the existing mature infrastructure. Handles running tests,…

Hey, that sounds really cool, and also sounds like it was a lot of work! As for point 2, we are planning at some point on making everything accessible via API and releasing a CLI, so a VSCode extension should definitely be possible.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#52

Post by pkkim »

hmaarrfk wrote: post #49

Thank you for tackling this critical problem for logic designiners. I think the tools available are much too old for fast paced workflows. From my experience attempting to get a similar workflow down for my company: I tried to use verilator a while back but ultimately I couldn't because it didn't have same constraints in the verilog language features that I was going to use in production. It doesn't even matter who w…

I really appreciate the feedback: these are all very valid points.

Bash is just an example; most people should make the test rule call the simulator executable directly or via a thin wrapper script. MyHDL is interesting too. Admittedly this is the first we've heard of it but we'll take a look.

We are working on supporting additional simulators in addition to Verilator.

Also, we are working on an API and command line tool so you can kick off test runs and view the results from the command line. This CLI tool should also support local test runs at some point.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#53

Post by qzcx »

mysteria wrote: post #43
doix wrote: post #33

I used to work at a fairly large fabless semiconductor company on the team that developed the internal tools for doing almost exactly what you were doing. > Tooling hasn’t kept up. The state of the art in collaborative debugging is to walk to a coworker’s desk and point to an error in a log file or waveform file. Each chip company rolls out its own tooling and infra to deal with this—this was Kay’s (one of our cofoun…

> On the topic of web viewing, do you know that engineers want this? In my experience, managers liked it because they could get an overview quickly, but the engineers hated it because it involved copy-pasting paths from the browser to their local tools. In my experience it's the opposite. While some firms issue Linux workstations to their engineers most use VDIs (and god forbid sometimes VNC) hosted in a datacenter t…

That's why I use vscode w/ remote ssh. Can't stand input lag on my typing.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#54

Post by qzcx »

pkkim wrote: post #51
qzcx wrote: post #37

As someone who's also done a lot of DV and DV tools, I love to see it. This gap was something I took away from attending DVCon last year and seeing all the papers from folks reinventing in the same verif tools. Feeling inspired after DVCon, I was sick of how annoying our test infrastructure was to interact with so I built a vscode extension as a front end to the existing mature infrastructure. Handles running tests,…

Hey, that sounds really cool, and also sounds like it was a lot of work! As for point 2, we are planning at some point on making everything accessible via API and releasing a CLI, so a VSCode extension should definitely be possible.

Honestly, way less work than you'd think. A couple of months of a few hours per week tinkering. Copilot taught me the typescript and the vscode api is very powerful and well documented. Being able to leverage other extensions already doing the heavy work is a huge benefit (such as DVT for identifying symbol definitions).

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#55

Post by pkkim »

croutons wrote: post #47

This is awesome! As a software person who dabbles in hardware, I cannot believe that HW folks put up with such arcane, slow, and cumbersome tools. I think anyone who’s critical of this idea has no idea how good they could be having it.

Thanks for the support!

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#56

Post by Lramseyer »

pkkim wrote: post #45
Lramseyer wrote: post #40

As a hardware developer, I love seeing EDA tools getting YC's attention and resources. When hardware designers talk about how terrible EDA tools are though (myself included,) I find that it's a lot of the pot calling the kettle black. Most semiconductor companies have the most ancient IT infrastructure and tooling. Like at my current company, we're still using perforce. Instead of using SSH, my coworkers VNC into a s…

Thanks for your thoughts! We are indeed planning to add support for other vendor tools, including the Synopsys, Cadence, and Siemens simulators. Cost for cloud vs on prem is very specific to design complexity. For the designs we're working with, we have seen that compute is cost effective on the cloud with respect to building out on-prem compute. We expect that to change as we support larger designs, and we have supp…

Great! Yeah, I imagine you guys have a lot on your plates. Looking forward to hearing more from you guys!
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