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Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

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Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#11

Post by pclmulqdq »

I'm about to pull a "dropbox" here, but I am aware of many companies that already do this inside their Git infrastructure. It's not that hard to do when you combine verilator, testbenches in software languages, and cloud CI intended for software. This is one of the big advantages of greenfield designs (and FPGA companies): you can set things up for Verilator and/or CocoTB natively, and then you get to use things like Github actions to do continuous verification.

If you can get the commercial simulators and full support for the awful, ass-backwards, industry-standard verification frameworks (eg UVM), there's a great business here, but the trouble is going to be in getting there.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#12

Post by pkkim »

pclmulqdq wrote: post #11

I'm about to pull a "dropbox" here, but I am aware of many companies that already do this inside their Git infrastructure. It's not that hard to do when you combine verilator, testbenches in software languages, and cloud CI intended for software. This is one of the big advantages of greenfield designs (and FPGA companies): you can set things up for Verilator and/or CocoTB natively, and then you get to use things like…

Thanks for the observations. It's true that every company that needs this eventually figures something out.

The difference is (a) our customers don't want to be in the devops business, and for startups especially it's a severe barrier to entry that we can make disappear, and (b) we are going to keep investing in our products (especially collaboration tools and integrations with waveforms, logs, etc) long past the point where a chip company would decide their internal tools are "good enough" (hint: they're generally not).

UVM support is one of the next items on our priority list.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#13

Post by pwarner »

zachbee wrote: post #2

I'm a professional chip designer. And as somebody who's had to build this sort of internal tooling myself, I think this sort of product is desperately needed! It makes sense to start with Verilator, because it's fast, easy, and open source, but it seems like it'll fall short on a lot of metrics. It seems like the big challenge is going to be making sure your tool can do everything that chip designers actually need to…

I worked with some chip design and verification folks. They were very tolerant of slow results, waiting for licenses or infrastructure. Their processes were just built around those constraints. They didn't seem to have interest in removing them.

As an impatient software developer it was very interesting.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#14

Post by reflexe »

Not sure i am following, what problem your product is trying to solve? helping to write tests/run the tests/just organizing tests as a part of the CI pipeline? How is it different than just running tests? (Or is it the platform to run tests on?) If you are trying to do CI for silicon, then what is your target market? From my experience, companies that design their own silicon are usually big enough to have their own custom pipeline for testing and verification and it would be quite difficult to convince them to switch. Smaller companies get help from larger companies in development and verification.

Do you have any tooling that won’t require the developer to write tests? (E.g. something that will ‘work’ with no effort from the developer’s POV - kind of sonarqube for vhdl/verilog)

In any case, good luck. Glad to see some HW-related startups.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#15

Post by pkkim »

karthityrion wrote: post #7

I might be missing something but how does the product reduce verification time? Isn't it just Verilator running on a cloud server? How does it help with debugging?

Hey, good question, thanks.

We speed up developers in two ways: For debugging individual tests, we have a web based log viewer and web based waveform viewer, so you can share test results or look at waves via a URL, instead of opening VNC. More holistically, we're building a chip focused workflow that will make tests first class -- infrastructure to track tests, and by extension measure design health, will be in one place, instead of implemented with a bunch of handrolled, bespoke tooling.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#16

Post by imakwana »

pkkim wrote: post #12
pclmulqdq wrote: post #11

I'm about to pull a "dropbox" here, but I am aware of many companies that already do this inside their Git infrastructure. It's not that hard to do when you combine verilator, testbenches in software languages, and cloud CI intended for software. This is one of the big advantages of greenfield designs (and FPGA companies): you can set things up for Verilator and/or CocoTB natively, and then you get to use things like…

Thanks for the observations. It's true that every company that needs this eventually figures something out. The difference is (a) our customers don't want to be in the devops business, and for startups especially it's a severe barrier to entry that we can make disappear, and (b) we are going to keep investing in our products (especially collaboration tools and integrations with waveforms, logs, etc) long past the poi…

I noticed there are some GitHub Repos actively working on enabling UVM on Verilator:

https://github.com/MikeCovrado/GettingVerilatorStartedWithUV...

It would be an amazing leap to enable UVM fully on Verilator. Looking forward to it.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#17

Post by pkkim »

reflexe wrote: post #14

Not sure i am following, what problem your product is trying to solve? helping to write tests/run the tests/just organizing tests as a part of the CI pipeline? How is it different than just running tests? (Or is it the platform to run tests on?) If you are trying to do CI for silicon, then what is your target market? From my experience, companies that design their own silicon are usually big enough to have their own…

Hey, thanks!

CI is one component of our platform. Most other CI tools are pretty agnostic about how tests are structured, though. We also integrate a way to structure your tests into groups so you can control when each test is called. For example, if one test out of 500 fails, it's super easy to rerun that one test with verbose logging and wave dumping enabled. We then also track test pass/fails over time, have tools to leave comments for coworkers on waveforms and logs in the browser like in Google Docs, etc.

Out of curiosity, what do you mean by "Smaller companies get help from larger companies in development and verification"?

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#18

Post by pkkim »

pwarner wrote: post #13
zachbee wrote: post #2

I'm a professional chip designer. And as somebody who's had to build this sort of internal tooling myself, I think this sort of product is desperately needed! It makes sense to start with Verilator, because it's fast, easy, and open source, but it seems like it'll fall short on a lot of metrics. It seems like the big challenge is going to be making sure your tool can do everything that chip designers actually need to…

I worked with some chip design and verification folks. They were very tolerant of slow results, waiting for licenses or infrastructure. Their processes were just built around those constraints. They didn't seem to have interest in removing them. As an impatient software developer it was very interesting.

Yeah, our team has experience in both hardware and software. DV engineers have a really hard time and we're trying to make it better.

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#19

Post by karthityrion »

pkkim wrote: post #15
karthityrion wrote: post #7

I might be missing something but how does the product reduce verification time? Isn't it just Verilator running on a cloud server? How does it help with debugging?

Hey, good question, thanks. We speed up developers in two ways: For debugging individual tests, we have a web based log viewer and web based waveform viewer, so you can share test results or look at waves via a URL, instead of opening VNC. More holistically, we're building a chip focused workflow that will make tests first class -- infrastructure to track tests, and by extension measure design health, will be in one…

Thank you! So will it be a web-based wave viewer and debugger?

Re: Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud

#20

Post by reflexe »

pkkim wrote: post #17
reflexe wrote: post #14

Not sure i am following, what problem your product is trying to solve? helping to write tests/run the tests/just organizing tests as a part of the CI pipeline? How is it different than just running tests? (Or is it the platform to run tests on?) If you are trying to do CI for silicon, then what is your target market? From my experience, companies that design their own silicon are usually big enough to have their own…

Hey, thanks! CI is one component of our platform. Most other CI tools are pretty agnostic about how tests are structured, though. We also integrate a way to structure your tests into groups so you can control when each test is called. For example, if one test out of 500 fails, it's super easy to rerun that one test with verbose logging and wave dumping enabled. We then also track test pass/fails over time, have tools…

In my experience in two HW companies that developed their own ASICs (one as a startup and one as a publicity traded company), we never developed any chip fully by ourself. In all of the cases there was another large company who helped to make the project work so we will actually end up with wafers.

If you are not at the scale of NVIDIA/intel and release a new silicon every other month, it is not worth it to recruit so many people for a relatively short period. However, I am not fully sure how involved they were in the pre-silicon verification process, but at least in some cases they were very involved in the development.

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