Calyx: Intermediate Language for Hardware Accelerators • Hacker News Board

Re: Calyx: Intermediate Language for Hardware Accelerators

#31

Post by rachitnigam » Tue, Feb 27, 2024, 5:22 PM UTC

vrinsd wrote: post #27

I'm always interested in new hardware-oriented DSLs, so great to see effort and work here. rachitnigam, do you have any example designs of "significant" complexity? I looked over the paper and saw your 2x2 array example -- I'm curious if you make this something like 100x100 or n x m, can that be done in parameterizable way? What about control-structures like bits to enable / disable functionality, etc? Also, do you p…

Yeah, we've been able to compile entire neural networks like GoogleNet etc. through Calyx. See: https://calebmkim.github.io/files/pubs/src.pdf

HLS-like languages are an input to Calyx. For example, we're currently building a Vivado alternative using Calyx and the frontend there does the pipelining for us. Calyx then goes in and performs a bunch of other optimizations.

A big edge we have is that Calyx supports both statically-scheduled circuits (where the latencies of things are known) and dynamically-scheduled circuits (where latency is not known). Because of this, we have been able to do optimizations in this new flow that take advantage of both.

Re: Calyx: Intermediate Language for Hardware Accelerators

#32

Post by rachitnigam » Tue, Feb 27, 2024, 5:24 PM UTC

BenoitP wrote: post #29

ipsum2 wrote: post #24

How does this compare to chisel?

From a glance: it seems like it is more specific for accelerators. Chisel deals in the general way, but Calyx seems to have primitives for wiring systolic arrays for example. If you plan to do an OoO CPU, choose Chisel. If you want to do a DSP or TPU, choose Calyx.

You can express full CPU designs in Calyx (in fact, we have) because it is a superset of a hardware description language. However, Calyx will probably not provide any substantial benefit in this case because there are not that many opportunities to optimize things.

The premise of Calyx is you're generating hardware designs from high-level code which has a lot more structure than arbitrary HDL code and the compiler will use that extra structure to automatically do optimizations that cannot be done over arbitrary HDL code.

Re: Calyx: Intermediate Language for Hardware Accelerators

#33

Post by vrinsd » Wed, Feb 28, 2024, 10:07 PM UTC

rachitnigam wrote: post #31

vrinsd wrote: post #27

I'm always interested in new hardware-oriented DSLs, so great to see effort and work here. rachitnigam, do you have any example designs of "significant" complexity? I looked over the paper and saw your 2x2 array example -- I'm curious if you make this something like 100x100 or n x m, can that be done in parameterizable way? What about control-structures like bits to enable / disable functionality, etc? Also, do you p…

Yeah, we've been able to compile entire neural networks like GoogleNet etc. through Calyx. See: https://calebmkim.github.io/files/pubs/src.pdf HLS-like languages are an input to Calyx. For example, we're currently building a Vivado alternative using Calyx and the frontend there does the pipelining for us. Calyx then goes in and performs a bunch of other optimizations. A big edge we have is that Calyx supports both st…

This is great to hear. It might be nice to bubble those examples up to your Github page along with some diagrams and logic/resource results after synthesis (i.e. how many LUTs, BRAM, etc).

It's easy for people to do a lot of naysaying, it's a lot harder to try and actually do something evolutionary, let alone revolutionary. Please keep posting with up-to-date results.