One that I haven’t acted on yet: virtual boss piñatas.
Ask HN: Let's generate some startup ideas in 2024
11–20 of 23 posts
Re: Ask HN: Let's generate some startup ideas in 2024
#12“The commish”. Online Monopoly game, but for sports. Multi personas - stadium owners, team owners, broadcasters, sponsors, etc.
Re: Ask HN: Let's generate some startup ideas in 2024
#13Earlier quoted context omitted.
"Put your kids on the blockchain", as in setting them up with a wallet from early on so that it can be accessed later?
No like proving they are your kids and not somebody else’s. It would also allow for more trusted adoption procedures. And let parents buy/sell children more securely without government intervention.
Like NFT for social security number
Re: Ask HN: Let's generate some startup ideas in 2024
#14A platform in which you can create blog posts with AI and post directly into your Wordpress blog page. I am bulding one in https://postbrainer.com
Re: Ask HN: Let's generate some startup ideas in 2024
#15A platform in which you can create blog posts with AI and post directly into your Wordpress blog page. I am bulding one in https://postbrainer.com
Firefox thinks that the site is a potential threat:
Firefox detected a potential security threat and did not continue to postbrainer.com. If you visit this site, attackers could try to steal information like your passwords, emails, or credit card details.
The certificate is not trusted because it is self-signed.
Re: Ask HN: Let's generate some startup ideas in 2024
#16Whispersync (Amazon's handoff product to switch from reading a Kindle book to listening to its Audible copy if you have both), but two-way for podcast episodes and blog posts.
Subscribe to podcast feeds and/or blog RSS feeds. Podcasts get transcribed by some AI tool. Written feeds get transformed into audio.
You can "highlight" in either one, using something like Snipd's system for podcast snipping (which you can easily go back and edit because you have a written transcript too).
I read much, much faster than I listen, even on 2x speed or higher, and I retain it better, so the killer feature to me is more the transcript of the podcast than the audio of the blog post.
Bonus points if it has e-reader-friendly pagination as a scroll option. And if I can self-host it if I want. And if I can export my notes.
If I knew how to build things at all, I'd be working on it right now.
Re: Ask HN: Let's generate some startup ideas in 2024
#17Job board with high posting fee and half the fee goes toward candidate that gets the job.
Re: Ask HN: Let's generate some startup ideas in 2024
#18A dating app where you have to meet in person. No photos or texting.
Maybe everyone is prevetted and there’s a service or AI that makes sure you’re compatible looks wise, etc.
Re: Ask HN: Let's generate some startup ideas in 2024
#19Earlier quoted context omitted.
I like this, want to brainstorm with me further? I raised $372.03 for my FPGA chip on my profile and I've only sketched out a rough mock prototype of what I want the architecture to be. So far, it works with any amount of silicon defects, can be up to the size of a silicon wafer, and the larger it is, the more it can reconfigure itself in parallel, which is directly proportional to its size growth.
I found your previous post - https://news.ycombinator.com/item?id=38170336 I find your ideas interesting, especially your strong interest in routing around any faults, but still ending up with a relatively usable compute fabric. My approach is much, much simpler.... just a grid of cells, with the programming lines unspecified. Each cell has a 4 bits in from their neighbors, a 4x4 LUT, a latch on each of the 4 bits of…
Are you making a pipelined FPGA architecture or a systolic array?
How would you improve my FPGA? I have two directions that I could take my FPGA architecture such as adding analog Logic Blocks and adding beamforming LUT interconnect.
Can you explain how you would go about getting an MVP manufactured?
Re: Ask HN: Let's generate some startup ideas in 2024
#20Earlier quoted context omitted.
I found your previous post - https://news.ycombinator.com/item?id=38170336 I find your ideas interesting, especially your strong interest in routing around any faults, but still ending up with a relatively usable compute fabric. My approach is much, much simpler.... just a grid of cells, with the programming lines unspecified. Each cell has a 4 bits in from their neighbors, a 4x4 LUT, a latch on each of the 4 bits of…
Are you making a pipelined FPGA architecture or a systolic array? How would you improve my FPGA? I have two directions that I could take my FPGA architecture such as adding analog Logic Blocks and adding beamforming LUT interconnect. Can you explain how you would go about getting an MVP manufactured?
If you look at them right, an FPGA is a bad systolic array. They're heterogeneous, or lumpy, the switching fabric makes them fast when you're trying to cut down on latency, but in terms of general purpose compute, it makes them horrible to program, as you have to solve the routing for a given chip architecture and its features and limitations.
A BitGrid is completely uniform, a grid of cells with I/O to each Cartesian neighbor. If you have a compiled program ready to load into the LUTs, it's easy to move things over a row or column, or flip it, rotate everything 90 degrees, etc. Routing around a bad cell should be trivial.
Because I add a latch to the I/O, and the clocking is in alternative phases, you can't have a race condition, it's stable. All "white" cells have I/O to black cells (which are latched at that time), and vice/versa.
This makes it very easy to reason about, while still being Turing complete. It also means that you can have 4 independent functions of the same 4 bits of input, if you need it, in a given cell. Because each cell is doing its compute directly on data, and all in parallel, you should be able to get at least 50% utilization out of the LUTs without too much effort on the part of a compiler.
If you have data flowing "right" on the grid through a number of cells, with carry and things sometimes going "up" and "down", you're not likely to use ALL of those signals. In that case, you could have a completely different stream of data and compute going "left" at the same time. It can get as tightly used as the compilers want to dedicate time to finding.
Google supported (and I think still supports) an open source chip shuttle program that will make a chip, provided the design is licensed open source. I intend to get the BitGrid design made through that channel. I'll likely prototype it on an FPGA along the way. I've already got the emulator, so I can start work on some form of language/compiler to use to program it.
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As for your design, I think that it would be helpful to know how many % of chip defects are in what layers of the chips. If metallization almost never fails, then just using wires all the way across the chip in an X/Y grid isn't that likely to be an issue that needs to be solved.
If the metallization does fail frequently, your design offers an advantage. However, any disabled section will effect propagation delays, which might eliminate the value of routing around damage.