Chisel: A Modern Hardware Design Language
11–20 of 78 posts
Re: Chisel: A Modern Hardware Design Language
#12Everytime I look at the examples, coming from a verilog background, it's strange to see the clock and reset are all implicit rather than explicit. The blinking led for example, while readable the link between the generated verilog with clock and reset is not clear. How are multi clock domains and Async CDCs handled? I've never used chisel so maybe this all is well managed, but not being explicit about the clock domai…
Re: Chisel: A Modern Hardware Design Language
#13Re: Chisel: A Modern Hardware Design Language
#140. https://stackoverflow.com/questions/53007782/what-benefits-d...
Re: Chisel: A Modern Hardware Design Language
#15It uses Dart instead of Scala.
Re: Chisel: A Modern Hardware Design Language
#16I've played with this and while I much prefer it to verilog (and even migen) it is still too implicit for me. Most of my time spent building VGA toy was wasted debugging wrong counter wrapping and similar. I would like to try out something where the register width and operation semantics (wrap, extend, saturate) have to be always explicit. Maybe it would turn out to be too annoying?
Try VHDL. It’s Ada heritage gives it that explicit feel.
Re: Chisel: A Modern Hardware Design Language
#17Not being a hardware person, when I heard “Hardware Design Language” I was thinking more along the lines of Snow White[1] - the idea of an open source industrial design language would be pretty interesting, something along the lines of Material UI but for hardware. 1. https://en.wikipedia.org/wiki/Snow_White_design_language
Re: Chisel: A Modern Hardware Design Language
#18I've said as much before but I find the issue with alternative HDLs Vs SystemVerilog is they concentrate on fixing annoying and frustrating things but don't address the really hard issues in hardware design and can actually make them harder. For example SystemVerilog has no real typing which sucks, so a typical thing to do is to build a massively improved type system for a new HDL. However in my experience good use o…
Re: Chisel: A Modern Hardware Design Language
#19Everytime I look at the examples, coming from a verilog background, it's strange to see the clock and reset are all implicit rather than explicit. The blinking led for example, while readable the link between the generated verilog with clock and reset is not clear. How are multi clock domains and Async CDCs handled? I've never used chisel so maybe this all is well managed, but not being explicit about the clock domai…
Their docs explain it. It’s sorta like “implicit this”. https://www.chisel-lang.org/docs/explanations/multi-clock
Re: Chisel: A Modern Hardware Design Language
#20Not being a hardware person, when I heard “Hardware Design Language” I was thinking more along the lines of Snow White[1] - the idea of an open source industrial design language would be pretty interesting, something along the lines of Material UI but for hardware. 1. https://en.wikipedia.org/wiki/Snow_White_design_language