Using Make – writing less Makefile
text.causal.agency
Using Make – writing less Makefile
1–10 of 200 posts
Re: Using Make – writing less Makefile
#2I like the man page format each post has on this website. A little hard to read, but very unique.
Re: Using Make – writing less Makefile
#3I like the man page format each post has on this website. A little hard to read, but very unique.
Yeah, 2023 and reflowing documents still isn't a thing. Yay
Re: Using Make – writing less Makefile
#4I like the man page format each post has on this website. A little hard to read, but very unique.
Yeah, 2023 and reflowing documents still isn't a thing. Yay
I read this on mobile and it felt pretty tedious. I wonder if maybe some minimal HTML could make the paragraphs reflow properly while still looking like a manpage everywhere.
Re: Using Make – writing less Makefile
#5It's unfortunate that most programmers only experience with make is automake/autoconf. This is fantastic.
Re: Using Make – writing less Makefile
#6If you want to write less makefile, you don't need to define foo. `foo` is an implicit target if foo.c is present.
You can use make in this form without a makefile even:
~ % echo '#include \nvoid main() { printf("OHAI\\n"); }' > ohai.c
~ % make CFLAGS=-DDEFINE_ME_A_MAKEFILE ohai
cc -DDEFINE_ME_A_MAKEFILE ohai.c -o ohai
~ % ./ohai
OHAIRe: Using Make – writing less Makefile
#7For larger programs, the compiler can also generate the dependency tree for incremental compilation: https://www.gnu.org/software/make/manual/html_node/Automatic...
Re: Using Make – writing less Makefile
#8With gnu make you don't even need OBJs for a simple directory in which all the .c files are compiled:
.SECONDEXPANSION
foo: $$(patsubst %.c,%.o,$$(wildcard *.c))
$(CC) $(LDFLAGS) $^ $(LDLIBS) -o $@
I make small Makefiles like this that ensure my local build environment is correct for the package, then call cmake.
Re: Using Make – writing less Makefile
#9Re: Using Make – writing less Makefile
#10If you want to write less makefile, you don't need to define foo. `foo` is an implicit target if foo.c is present. You can use make in this form without a makefile even: ~ % echo '#include \nvoid main() { printf("OHAI\\n"); }' > ohai.c ~ % make CFLAGS=-DDEFINE_ME_A_MAKEFILE ohai cc -DDEFINE_ME_A_MAKEFILE ohai.c -o ohai ~ % ./ohai OHAI
In that case why call make at all?