Even a laptop can run RAM externally thanks to CXL
21–30 of 85 posts
Re: Even a laptop can run RAM externally thanks to CXL
#22The purpose of CXL is to allow for memory coherency between different CXL devices. To quote the spec on type 2 devices:
> CXL Type 2 devices, in addition to fully coherent cache, also have memory, for example DDR, High-Bandwidth Memory (HBM), etc., attached to the device. These devices execute against memory, but their performance comes from having massive bandwidth between the accelerator and device-attached memory. The main goal for CXL is to provide a means for the Host to push operands into device-attached memory and for the Host to pull results out of device-attached memory such that it does not add software and hardware cost that offsets the benefit of the accelerator.
There's some cool things you can do with CXL, like resurrecting the whole persistent memory idea with low-latency flash, making hardware offload devices more capable since you now get free cache coherency, and a whole bunch of other stuff.
But yes, it's really not for consumer use-cases. The applications I've seen colleagues work on are mostly enterprise stuff like cool RDMA integrations, cache-coherent flash, and more I can't talk about here.
Re: Even a laptop can run RAM externally thanks to CXL
#23This wasn't mentioned in the article but CXL Stands for Compute Express Link which is an open standard, CPU-to-Device Interconnect, I guess they're on v3.0 now. First I had heard of it as well. 3.9GB/s on the low end and as high as 121.0GB/s with the latest 16x 3.0 spec over serial connection https://www.computeexpresslink.org/about-cxl https://en.wikipedia.org/wiki/Compute_Express_Link
It might work for laptops, but it is not the main goal and it might be only Framework who will do something in that direction.
Re: Even a laptop can run RAM externally thanks to CXL
#24Re: Even a laptop can run RAM externally thanks to CXL
#25How much do one of these cost and is the memory persistent?
Re: Even a laptop can run RAM externally thanks to CXL
#26The slowest clock speed for DDR5 is 2,000Mhz or 0.5ns per cycle. At 2/3c, electricity should be able to travel about 10cm max in one cycle. I suppose 4Ghz RAM would be only 5cm. Is having an external unit with much greater than 10cm of copper travel ultimately a limiting factor here with modern day RAM speeds?
I'm personally now imagining a specialized database appliance which takes the role of the whole of the pager and buffer pool management from a DB (or KV store or whatever); a physical box which ties secondary storage arrays + large quantities of RAM + buffer pool mgmt firmware together on a box, then connect to host system via CXL. Host system does query planning end execution and everything else...
Is anybody doing this? Does anybody want to found a startup with me to do this?
Re: Even a laptop can run RAM externally thanks to CXL
#27If CXL is not being used by servers, will it ever become an offering for laptops?
Re: Even a laptop can run RAM externally thanks to CXL
#28The slowest clock speed for DDR5 is 2,000Mhz or 0.5ns per cycle. At 2/3c, electricity should be able to travel about 10cm max in one cycle. I suppose 4Ghz RAM would be only 5cm. Is having an external unit with much greater than 10cm of copper travel ultimately a limiting factor here with modern day RAM speeds?
Note that modern RAM protocols assume that multiple bits are in the transmission line that is the wires connecting your CPU to RAM. Electrical Engineers since at least DDR2, probably earlier, need to ensure that all lines are delay matched to about 100picoseconds. That is, in DDR2, if DataBit#1 takes 1.1nanoseconds from start-of-wire to end-of-wire, then all other bits must be somewhere between 1.0ns to 1.2ns in leng…
Re: Even a laptop can run RAM externally thanks to CXL
#29The slowest clock speed for DDR5 is 2,000Mhz or 0.5ns per cycle. At 2/3c, electricity should be able to travel about 10cm max in one cycle. I suppose 4Ghz RAM would be only 5cm. Is having an external unit with much greater than 10cm of copper travel ultimately a limiting factor here with modern day RAM speeds?
The article seems to reference having external AI etc accelerators colocated with the RAM they use, but then tied to a host machine via CXL. So that makes a certain amount of sense. Latency sensitive stuff happens co-located with the RAM, and then you just take advantage of throughput back to the host. I'm personally now imagining a specialized database appliance which takes the role of the whole of the pager and buf…