Actually if the IC design tools would be FOSS, the cost of new designs would decrease considerably, even up to two times.
The cost of the subscriptions to the design tools provided by Cadence, Synopsis, Siemens (Mentor) and a few others is ridiculously high and it can contribute with many millions of $ to the design cost of a state-of-the-art chip.
The design tools themselves have been improved extremely slowly and they are of a quite low quality for so expensive professional tools. In an open-source environment it would be easy to make much better alternatives.
The reason that only a few timid attempts exist to provide alternatives for only some parts of a complete toolchain, is that the semiconductor manufacturers, like TSMC, do not provide public information about the exact data that they need as input for manufacturing, about the design rules that must be implemented for valid designs and about the characteristics of their processes that must be known for simulations.
All this information is available only to big companies like Synopsis, Cadence etc. and this perpetuates their monopoly and their ability of extracting huge amounts of money with minimal software development work, from all the companies that design ICs.
While the companies that design ICs are not happy for this huge rent that they pay for the design tools, they are also extremely risk-averse and they do not want to make any change in their design workflows, no matter how small, that might increase the risks of failure in a designed chip. Because of this there are no chances of replacing the incumbents with open-source tools, at least not in the big established companies that design chips.