Related Chuck Moore talk: "Programming a 144 Computer Chip to Minimize Power" (2013) https://www.youtube.com/watch?v=0PclgBd6_Zs How Forth powers ultra-low power computers: "GreenArrays is shipping its 144-core asynchronous chip that needs little energy (7 pJ/inst). Idle cores use no power (100 nW). Active ones (4 mW) run fast (666 Mips), then wait for communication (idle)."
I genuinely wonder if this topology won't make a come back in the coming years.
Unfortunately, GA don’t seem to have gotten the memo about cheap entry-level dev tools that the microcontroller world has been circulating since 2010 or so. At the prices they charge for their devboards, you wouldn’t really get one just to play with, even if the chips themselves are actually somewhat cheap compared to getting the same amount of compute on an FPGA.
(It’s $500 per devboard and $20 per chip, with each chip capable of 2e9 16-bit multiplies/sec. Somebody[1] is selling a breakout board with only the chip for a much more reasonable price of $35, but you’ll need to figure out how to wire up the thing yourself.)
Charles Moore is known for aggressively patenting his hardware, though. (Well, he and every other modern chip designer.) So we might not get to see anybody else do this stuff for a long, long time. Adapteva’s Epiphany/Parallella design used a broadly similar idea with an explicit grid interconnect and also aimed for a piece of the FPGA/ASIC pie, but they had much beefier, synchronous cores with separate message routers attached to them.
[1] https://schmartboard.com/schmartboard-ez-qfn-88-pins-0-4mm-p...