Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
1–10 of 29 posts
Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#2Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#3i get displays are not the realm of single digit cents 4 bitters or something. but i can think of other mcus more constrained w probably still enough flash and fast enough SPI bus and dma that would be a much better showing.
i guess i feel the pico is overkill, but at any rate this is mostly unfair because its not the toolkits target market in the first place
Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#4the "if we can port it to the constrained pico we can make it run on any mcu" bit made me wat. the pico is a pretty large mcu really. i get displays are not the realm of single digit cents 4 bitters or something. but i can think of other mcus more constrained w probably still enough flash and fast enough SPI bus and dma that would be a much better showing. i guess i feel the pico is overkill, but at any rate this is…
I feel people that don't usually work mit MCUs think a Pico2040 or ESP32 is a crazy constrained environment, when those are really rather luxurious. I'm not sure how much it matters - maybe its like complaining about Elektron while Slack (deservedly) succeeds.
Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#5Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#6Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#7Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#8If you get to the inlined video and think it looks a little sluggish, keep reading - they later implemented DMA to speed it up. Here's the link to this video showing it: https://youtube.com/watch?v=dkBwNocItGs
Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#9Meanwhile we have this laggy mess...
Re: Porting the Slint UI Toolkit to a Microcontroller with 264K RAM
#10It's funny to compare "modern" with microcomputers of the old. Original Amiga 500 ran with 512kB RAM, with OS requiring only 256kB (as in "you could run something other than just OS on that"). Meanwhile we have this laggy mess...
This is a slow SPI bus with the cpu needing to push W x H x BPP pixels and with a 320x240 16bpp that comes out to 9 million bytes/sec for 60fps or 4.5 million for 30 fps. Cortex M0 I believe has 4 cycles for load and store, so even if you had a perfect parallel 16 bit bus where you could do 1 load + 1 store to send a pixel, that comes out to a best case ~80 fps @ 100MHz with 100% cpu utilization (i.e you could do nothing else on that cpu, not even serve interrupts). Another core wont help much because it shares the memory bus, and fill rate is the bottleneck here.
There's a good reason why we have dedicated chips for pushing framebuffer -> lcd physical pixels even back in the 80s.