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RVVM – The RISC-V Virtual Machine

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Re: RVVM – The RISC-V Virtual Machine

#5

Instruction interpreter is nicely human-readable: https://github.com/LekKit/RVVM/blob/staging/src/cpu/riscv_i....

The RISC-V isa is specifically designed to be nice and regular and easy to decode, and work with, which definitely shows here (also in the RTL code if you look at some of the well designed RISC-V cores)

Of course, bot x86 and Arm started like that as well - but after 20+ years of evolution, they have to drag along a lot of history. (and one never really takes things away from an ISA, you only add new features, and at best deprecate old ones).

That said, with the extensibility of the ISA in mind as a design principle, I do have good hopes, RISC-V will stand the test of time reasonable well in that sense...

Re: RVVM – The RISC-V Virtual Machine

#6

How is this different from QEMU which also supports RISC-V 32|64 fairly well.

I had the exact same question. I do like this - it's nice and ambitious to build something like this from the ground up. Looking at the todo list though, they still have quite some work to get to parity with qemu...

Re: RVVM – The RISC-V Virtual Machine

#9

How is this different from QEMU which also supports RISC-V 32|64 fairly well.

It's supposed to be faster, smaller, and easier to integrate into other applications and systems than QEMU. In my tests it's sometimes faster and definitely smaller and simpler.

I think it's also easier to build as WASM and run in a browser.

I don't think 100% feature parity with QEMU is a goal.

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