RVVM – The RISC-V Virtual Machine
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RVVM – The RISC-V Virtual Machine
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Re: RVVM – The RISC-V Virtual Machine
#2Re: RVVM – The RISC-V Virtual Machine
#3Re: RVVM – The RISC-V Virtual Machine
#4Re: RVVM – The RISC-V Virtual Machine
#5Instruction interpreter is nicely human-readable: https://github.com/LekKit/RVVM/blob/staging/src/cpu/riscv_i....
Of course, bot x86 and Arm started like that as well - but after 20+ years of evolution, they have to drag along a lot of history. (and one never really takes things away from an ISA, you only add new features, and at best deprecate old ones).
That said, with the extensibility of the ISA in mind as a design principle, I do have good hopes, RISC-V will stand the test of time reasonable well in that sense...
Re: RVVM – The RISC-V Virtual Machine
#6How is this different from QEMU which also supports RISC-V 32|64 fairly well.
Re: RVVM – The RISC-V Virtual Machine
#7[flagged]
Re: RVVM – The RISC-V Virtual Machine
#8Re: RVVM – The RISC-V Virtual Machine
#9How is this different from QEMU which also supports RISC-V 32|64 fairly well.
I think it's also easier to build as WASM and run in a browser.
I don't think 100% feature parity with QEMU is a goal.
Re: RVVM – The RISC-V Virtual Machine
#10[flagged]
Does removing an icon of cigarette make you less sick and help save millions of lives?