Earlier quoted context omitted.
Because the added 3D V-cache increases heat. That's also why the X3D variants have lower clocks than the non-X3D versions. Two CCDs with V-cache is apparently too hot.
Previously that wasn't the issue, the issue (according to AMD) was that there was a huge interchip communication bottleneck with the extra L3 on both chips. If thats fixed, then AMD is just being cheap :P
https://www.anandtech.com/show/17323/amd-releases-milan-x-cp...
> Critically, AMD has opted to equip all of their new V-cache EPYC chips with the maximum 768 MB of L3 cache, which in turn means all 8 CCDs must be present, from the top SKU (EPYC 7773X) to the bottom SKU (EPYC 7373X). Instead, AMD will be varying the number of CPU cores enabled in each CCD.
(unff 768MB of cache)
afaik AMD has said the voltage is one limit because they share a voltage rail, so, you can't go outside the operating limits of the v-cache die. But thermals are another because the cache die does limit thermal transfer out of the CCD as well. They did shave it down (to maintain package height) which helps somewhat but I think it does run at least a bit hotter due to the separation between dies. But voltage is, afaik, the primary limitation, and I've never heard of cache coherency as being the problem.
I don't think they're lying about the cache die hurting clocks, that's obviously true from 5800X vs 5800X3D and lower clocks hurts performance in some applications, so they're legitimately trying to offer the best all-around-performer they can as a general-purpose CPU. But I also think they're being very careful about how much they let Ryzen cannibalize their Epyc X3D lineup too, and doing their best to salami-slice this into multiple releases.
There's no reason they couldn't have done 5900X3D last gen, and I bet eventually we will see a dual-cache-die release too. There is (based on Epyc) pretty obviously no technical limitation here, they just don't want to sell it to you right now. You can make excuses like "oh the market just isn't there" but... I think they will do it eventually. For now they are just using it to distinguish between Ryzen and Epyc, previously it was if you wanted >8 cores, now it is 12C and 16C but only one cache die, in a gen or three they will throw in the towel and let you buy all-cache-die configs if that's what you want.