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Here I was, hoping for ternary RAM: 1/0/-1. Didn't Burroughs field a ternary machine, once?
Ternary is fun but hard to integrate with existing systems. The headline made me think about storing two bits per cell, like MLC flash does, with 4 levels of charge instead if 2.
Here I was, hoping for ternary RAM: 1/0/-1. Didn't Burroughs field a ternary machine, once?
Earlier quoted context omitted.
Ternary is fun but hard to integrate with existing systems. The headline made me think about storing two bits per cell, like MLC flash does, with 4 levels of charge instead if 2.
Can’t you use ternary internally but exposed binary to the system?
Signalling systems that don't divide cleanly into a number of bits are more complicated to work with; you need to group bits together into another group of terts[0] and assign states to each. It's less like "picking the bits between the bits out" and more like MFM/GCR encoding for magnetic media.
[0] Ternary digits. No clue what the official name is for these but I am not going to go with the obvious choice.
Here I was, hoping for ternary RAM: 1/0/-1. Didn't Burroughs field a ternary machine, once?
Ternary is fun but hard to integrate with existing systems. The headline made me think about storing two bits per cell, like MLC flash does, with 4 levels of charge instead if 2.
Alas, sensing the contents of a DRAM cell in the time allotted is already a tough ask. Having to discriminate between multiple voltage levels would surely make have a nasty latency impact.
OTOH, I believe DRAM senses entire rows at a time -- so after that latency hit, bandwidth might be unchanged.
Any idea if it is even possible with existing capacitive DRAM cells?
This is a short article about allowing RAM sizes that aren't powers of 2, like 24 GB or 48 GB instead of just the steps 8 GB, 16 GB, 32 GB. I initially thought this was going to be about using multiple states on the data pins to encode more bits per clock.
This is the least exciting news I’ve read in my life.
Right. Just what we needed, more product differentiation in RAM. Like Intel's 22 versions of the same basic CPU. 10% faster! 2x cache! ...
This has the potential to noticeably reduce costs in many cases.
Downvoting avalanche in 3...2..
Earlier quoted context omitted.
Right. Just what we needed, more product differentiation in RAM. Like Intel's 22 versions of the same basic CPU. 10% faster! 2x cache! ...
24GB and 48GB DIMMs are useful, and that's what this is about-- allowing non-power-of-2 sizes (in this case, 3x a power-of-2 is now allowed). This has the potential to noticeably reduce costs in many cases.