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Off topic: I am looking for the hardware programing manual of Zen IOMMU (to map bus address to physical address), I cannot find it or what???
The latest revision is from October 2022, so I assume that the many changes that have been incorporated into this revision are applicable to Zen 4: https://www.amd.com/en/support/tech-docs/amd-io-virtualizati...
Thx...
Apparently "CCD" stands for "core-complex die", a dumb acronym that just means "chip with cores", and different from the other "chip with i/o interconnect" you also get in a module. It is annoyingly rare to find anybody expanding this acronym. A meaningful definition of "CCX" is harder to find.
Zen 4 increases the CCX size to 8, so each CCD only has one.
I can't remember exactly how Zen 1 worked but I think it was different.
I'd really like to see more info on the desktop G APU's. I'm not even sure if they're making a Dragon Range desktop APU, but it's what I personally am most interested in (I get that the 7000 series have fairly meager integrated graphics as is). I realise it's a relatively unimportant market segment for them, but some info either way would be nice regardless.
Apparently "CCD" stands for "core-complex die", a dumb acronym that just means "chip with cores", and different from the other "chip with i/o interconnect" you also get in a module. It is annoyingly rare to find anybody expanding this acronym. A meaningful definition of "CCX" is harder to find.
CCX or core complex is a lower level grouping of cores. On Zen 2/3 the CCX would have 4 cores on a little ring bus. A full 8-core CCD would then have two of those 4-core CCXs connected via infinity fabric. The inter-CCD connections were also made with infinity fabric between the CCXs. Zen 4 increases the CCX size to 8, so each CCD only has one. I can't remember exactly how Zen 1 worked but I think it was different.
Apparently "CCD" stands for "core-complex die", a dumb acronym that just means "chip with cores", and different from the other "chip with i/o interconnect" you also get in a module. It is annoyingly rare to find anybody expanding this acronym. A meaningful definition of "CCX" is harder to find.
CCX or core complex is a lower level grouping of cores. On Zen 2/3 the CCX would have 4 cores on a little ring bus. A full 8-core CCD would then have two of those 4-core CCXs connected via infinity fabric. The inter-CCD connections were also made with infinity fabric between the CCXs. Zen 4 increases the CCX size to 8, so each CCD only has one. I can't remember exactly how Zen 1 worked but I think it was different.
5950X hit its highest clocks on cores 1 and 4. Both are located on the first CCD. My 3950X clocked highest on cores 4 and 5. Both are also on the first CCD. This is a curious pattern. Perhaps AMD is only binning one CCD to hit the maximum boost clocks on 16 core parts. I have 5950X and saw this pattern, the fastest cores are though 2nd and 6th (starting from 0). I don't remember exact values from testing (with stress…
AMD binning independently works of functioning cores; having all 8 cores working does not mean it magically bins higher. AMD has not commented publicly on this, but it is generally believed there are two Epyc bins (one for high perf, one for low voltage, both exceptional quality), one high quality Ryzen bin, and one low quality bin.
?950x contains one Epyc quality + one high quality; x models contain high quality dies (in addition to being binned for broken cores in 6 core-based models independent of clock speed binning), non-x using lower quality dies. Threadrippers are bin-selected similarly to ?950xs.
All 6 core Zen 2 chips that were sold were 3+3, never 4+2/2+4.
The only exception to the above binning is a single 4 core non-APU Zen 2 existed, using the very few dies where an entire CCX was dead in the CCD, but the other CCX worked. This also mean half the L3 was dead (as the L3 was split per CCX, and wasn't CCD wide). With Zen 3 and 4, this chip can't exist as they are single CCX (all 8 cores) per CCD.
Die binning, however, isn't magical. ?800x record-setting overclocks are only a smidgen behind record-setting ?590x per-chiplet overclocks.
Earlier quoted context omitted.
This would make sense right? You probably can't run all cores at max turbo frequency before hitting power and thermal limits. So dividing chiplets based on binning would result in good performance for 1-8 -threaded tasks while reducing chip lottery. (But it's possible there are other reasons for the discrepancy)
Is there optimization being done by AMD to locate the best performing chiplet on the best possible place on the bus?
I'd really like to see more info on the desktop G APU's. I'm not even sure if they're making a Dragon Range desktop APU, but it's what I personally am most interested in (I get that the 7000 series have fairly meager integrated graphics as is). I realise it's a relatively unimportant market segment for them, but some info either way would be nice regardless.
I thought they might release a desktop Rembrandt in the $100-200 range but they haven't, probably because AM5 motherboards are so expensive. They may or may not release Phoenix on AM5 later this year.
5950X hit its highest clocks on cores 1 and 4. Both are located on the first CCD. My 3950X clocked highest on cores 4 and 5. Both are also on the first CCD. This is a curious pattern. Perhaps AMD is only binning one CCD to hit the maximum boost clocks on 16 core parts. I have 5950X and saw this pattern, the fastest cores are though 2nd and 6th (starting from 0). I don't remember exact values from testing (with stress…
Could it be a simpler explanation in that the thermos of cores 1 & 4 are better than where other cores are located?