RISC vs. CISC: The Post-RISC Era (1999)
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RISC vs. CISC: The Post-RISC Era (1999)
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Re: RISC vs. CISC: The Post-RISC Era (1999)
#2It's a great submission, but please don't post archive links to HN when there's a live version of the original available. You're welcome to put the archive link in a comemnt; lots of people do that.
We changed the URL from https://web.archive.org/web/19991129051550/http://arstechnic....
Re: RISC vs. CISC: The Post-RISC Era (1999)
#3I really enjoy reading Jon's book, inside the machine.
Re: RISC vs. CISC: The Post-RISC Era (1999)
#4It's a great submission, but please don't post archive links to HN when there's a live version of the original available. You're welcome to put the archive link in a comemnt; lots of people do that. We changed the URL from https://web.archive.org/web/19991129051550/http://arstechnic... .
Sorry for that. At first I found a broken, unreadable version of the article[1] and I guess I assumed they don't have a better copy.
[1] - https://archive.arstechnica.com/cpu/4q99/risc-cisc/rvc-1.htm...
Re: RISC vs. CISC: The Post-RISC Era (1999)
#5> [Editor's note: this example actually finds 20^4, not 20^3. I'll correct it when the load on the server goes down. Still, it serves its purpose.
I guess the load on the server has yet to abate for 24 years.
Re: RISC vs. CISC: The Post-RISC Era (1999)
#6It's a great submission, but please don't post archive links to HN when there's a live version of the original available. You're welcome to put the archive link in a comemnt; lots of people do that. We changed the URL from https://web.archive.org/web/19991129051550/http://arstechnic... .
Sorry for that. At first I found a broken, unreadable version of the article[1] and I guess I assumed they don't have a better copy. [1] - https://archive.arstechnica.com/cpu/4q99/risc-cisc/rvc-1.htm...
No worries! The Google doth not always deal the same results.
Re: RISC vs. CISC: The Post-RISC Era (1999)
#7During a recent conference I attended, a keynote speaker discussed their idea of having CPUs with at least 10,000 RISC-V cores and servers with one million RISC-V cores [1].
The idea is appealing, but how feasible is it and how does RISC make this possible or useful? I'm just curious what people think about this.
[1]: https://www.microarch.org/micro55/media/keynote_ditzel.pdf
Re: RISC vs. CISC: The Post-RISC Era (1999)
#8> [Editor's note: this example actually finds 20^4, not 20^3. I'll correct it when the load on the server goes down. Still, it serves its purpose. I guess the load on the server has yet to abate for 24 years.
Wait, why would he need to wait for the load to go down before making a change? What am I missing, was it normal back then?
Re: RISC vs. CISC: The Post-RISC Era (1999)
#9> [Editor's note: this example actually finds 20^4, not 20^3. I'll correct it when the load on the server goes down. Still, it serves its purpose. I guess the load on the server has yet to abate for 24 years.
Wait, why would he need to wait for the load to go down before making a change? What am I missing, was it normal back then?
It might invalidate a bunch of caches and increase load even more.
Re: RISC vs. CISC: The Post-RISC Era (1999)
#10During a recent conference I attended, a keynote speaker discussed their idea of having CPUs with at least 10,000 RISC-V cores and servers with one million RISC-V cores [1]. The idea is appealing, but how feasible is it and how does RISC make this possible or useful? I'm just curious what people think about this. [1]: https://www.microarch.org/micro55/media/keynote_ditzel.pdf
The IO and RAM for that many cores would be a bottleneck. If you manage to keep everything local to a core or a group of cores then you'll severely constrain the kind of programs you can run.