11–20 of 21 posts
All code is open source! - https://github.com/fyquah/hardcaml_zprize
(Disclaimer: I'm one of the authors of the above blogpost)
(Edit: Added link to source code)
https://zprize.hardcaml.com contains a detailed technical write-up, which includes an overview of the MSMs and NTTs algorithms, some well-known methods to accelerate them (Pippenger's algorithm, Cooley-Tukey etc.) and a description of our implementation. All code is open source! - https://github.com/fyquah/hardcaml_zprize (Disclaimer: I'm one of the authors of the above blogpost) (Edit: Added link to source code)
https://zprize.hardcaml.com contains a detailed technical write-up, which includes an overview of the MSMs and NTTs algorithms, some well-known methods to accelerate them (Pippenger's algorithm, Cooley-Tukey etc.) and a description of our implementation. All code is open source! - https://github.com/fyquah/hardcaml_zprize (Disclaimer: I'm one of the authors of the above blogpost) (Edit: Added link to source code)
I looked at simple examples (counters, fibonacci generator) of hardcaml in the github repo, but I don't see any obvious advantages over systemverilog, verilog, or VHDL (the industry standard languages). Why would one use hardcaml over these?
Earlier quoted context omitted.
I looked at simple examples (counters, fibonacci generator) of hardcaml in the github repo, but I don't see any obvious advantages over systemverilog, verilog, or VHDL (the industry standard languages). Why would one use hardcaml over these?
But does VHDL work for FPGA?
https://zprize.hardcaml.com contains a detailed technical write-up, which includes an overview of the MSMs and NTTs algorithms, some well-known methods to accelerate them (Pippenger's algorithm, Cooley-Tukey etc.) and a description of our implementation. All code is open source! - https://github.com/fyquah/hardcaml_zprize (Disclaimer: I'm one of the authors of the above blogpost) (Edit: Added link to source code)
I looked at simple examples (counters, fibonacci generator) of hardcaml in the github repo, but I don't see any obvious advantages over systemverilog, verilog, or VHDL (the industry standard languages). Why would one use hardcaml over these?
> We believe by using Hardcaml we were able to more efficiently and robustly come up with designs in the short competition period
So, the authors seem to believe they are more productive in it than other languages, and seem to be positioning it as a competitive advantage.
The assumption of a trusted setup phase makes zkSNARKs somewhat obscure to use. Definitely, it does not fit for making evidence for voting where an adversary could have rigged a setup phase allowing to issue votes as sees fit.
So far, there have been ceremonies which invite anyone to join who wants to, and anyone who participated and destroyed their own key knows that the trusted setup isn't compromised.
An entire community could participate for their local votes and they could each destroy their own key in order to have confidence in the result.
if anyone here has run FPGA's specifically, at this sort of scale, i'd love to talk to them.
The assumption of a trusted setup phase makes zkSNARKs somewhat obscure to use. Definitely, it does not fit for making evidence for voting where an adversary could have rigged a setup phase allowing to issue votes as sees fit.
You can include a very large set of people in the trusted setup, and if even one of them destroys their key the system is safe. So far, there have been ceremonies which invite anyone to join who wants to, and anyone who participated and destroyed their own key knows that the trusted setup isn't compromised. An entire community could participate for their local votes and they could each destroy their own key in order…
> An entire community could participate for their local votes and they could each destroy their own key in order to have confidence in the result.
Two problems. Dishonest voters spoil the process. Synchronically running multiparty ceremony between all participants at the same time (what if the voter could not make it, what if the server gets a DDOS attack in the process).
Earlier quoted context omitted.
I looked at simple examples (counters, fibonacci generator) of hardcaml in the github repo, but I don't see any obvious advantages over systemverilog, verilog, or VHDL (the industry standard languages). Why would one use hardcaml over these?
From the article: > We believe by using Hardcaml we were able to more efficiently and robustly come up with designs in the short competition period So, the authors seem to believe they are more productive in it than other languages, and seem to be positioning it as a competitive advantage.