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Custom Processing Unit: Hook, patch, and trace microcode at the software level
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Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#12I sometimes wonder if not these CPUs are just waiting to have their power unleashed. Almost like FPGAs, they could be reprogrammed to have custom instructions by someone skilled.
This wouldn't actually help in common workloads, because the instructions that already exist are typically better than what you can achieve with microcode. The reason for the RISC revolution was the understanding that there are fairly strict limits of what you can achieve in a single instruction if you want your cpu to be fast. An instruction that does some complex task that you need done is not really going to be an…
It makes sense what you say, but I still have doubts. Are you saying that not all x86 instructions are implemented in microcode? And wouldn't shader language be a perfect target for custom microcode, etc.
Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#13Earlier quoted context omitted.
This wouldn't actually help in common workloads, because the instructions that already exist are typically better than what you can achieve with microcode. The reason for the RISC revolution was the understanding that there are fairly strict limits of what you can achieve in a single instruction if you want your cpu to be fast. An instruction that does some complex task that you need done is not really going to be an…
It makes sense what you say, but I still have doubts. Are you saying that not all x86 instructions are implemented in microcode? And wouldn't shader language be a perfect target for custom microcode, etc.
> Are you saying that not all x86 instructions are implemented in microcode?
If you look at discussions about the instruction decoder of Intel processors, you often see it mentioned that they have something like three "simple" decoders and one "complex" decoder. The main difference is that the "complex" decoder is the only one which can decode instructions implemented in microcode (dispatching micro-operations from the microcode ROM), while the "simple" decoders can only output micro-operations directly (using something similar to hard-wired pattern matching on the instruction). So yes, many x86 instructions are not implemented in microcode.
Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#14I sometimes wonder if not these CPUs are just waiting to have their power unleashed. Almost like FPGAs, they could be reprogrammed to have custom instructions by someone skilled.
These already exist in niche markets, they've stayed niche for a reason
Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#15Does this help us getting rid of IME?
You want to inspect the management engine not replace it.
The management engine does do useful stuff the issue is that we don't know what else it does too.
Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#16Earlier quoted context omitted.
This wouldn't actually help in common workloads, because the instructions that already exist are typically better than what you can achieve with microcode. The reason for the RISC revolution was the understanding that there are fairly strict limits of what you can achieve in a single instruction if you want your cpu to be fast. An instruction that does some complex task that you need done is not really going to be an…
It makes sense what you say, but I still have doubts. Are you saying that not all x86 instructions are implemented in microcode? And wouldn't shader language be a perfect target for custom microcode, etc.
The term microcode has become muddled in that you have microcode for implementing highly complex instructions and "microcode" as-in an internal target that X86 instructions are translated into.
Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#17Earlier quoted context omitted.
It makes sense what you say, but I still have doubts. Are you saying that not all x86 instructions are implemented in microcode? And wouldn't shader language be a perfect target for custom microcode, etc.
The term microcode has become muddled in that you have microcode for implementing highly complex instructions and "microcode" as-in an internal target that X86 instructions are translated into.
The internal instruction format is commonly called micro-ops / uops. But easy to confuse those terms.
Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#18One of my first paid gigs was to write a debugger for a RIP implemented in 2900 bitslice. It was a specialized SIMD architecture. The debugger was written in C and ran on the bootloader processor, which I recall being a 68k. Having taken an architecture course as an undergrad I sort of knew what I was doing, and microcode is inherently simple compared to, for example, 64-bit x86. I recall thinking "this is what a really wide PDP-11 would be like." The project was also interesting in that my customer was one person: The guy who designed the processor and who was writing the microcode.
Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#19I sometimes wonder if not these CPUs are just waiting to have their power unleashed. Almost like FPGAs, they could be reprogrammed to have custom instructions by someone skilled.
This wouldn't actually help in common workloads, because the instructions that already exist are typically better than what you can achieve with microcode. The reason for the RISC revolution was the understanding that there are fairly strict limits of what you can achieve in a single instruction if you want your cpu to be fast. An instruction that does some complex task that you need done is not really going to be an…
Could one add the AES-NI instruction to Intel CPUs that lacked it using purely microcode? Would it be a speedup compared to encoding one round of AES using regular instructions?
Re: Custom Processing Unit: Hook, patch, and trace microcode at the software level
#20Earlier quoted context omitted.
The term microcode has become muddled in that you have microcode for implementing highly complex instructions and "microcode" as-in an internal target that X86 instructions are translated into.
The internal instruction format is commonly called micro-ops / uops. But easy to confuse those terms.
I know, however lots of people make it up as they go along.