181–190 of 323 posts
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That's not true. Compare the 8+ Gen 1 (TSMC N4) against A15 (TSMC N5).
Qualcomm prioritizes cost over performance and it shows. Look at AMD for a performance comparison.
You're looking in the wrong place. The magic comes from TSMC, not Apple. Apple's major innovation is in using their unrivaled bank account to pay TSMC for exclusivity on their newest fabrication technology. As competitors gain access to that TSMC technology they will match or beat Apple's performance. And if Intel succeeds in reclaiming the fabrication technology lead from TSMC (we'll see) then Intel will beat Apple'…
This is just absolutely incorrect. Design is over half the battle, look at Qualcomm n5 performance vs Apple M1 on n5 performance. It's not even comparable in anyway. Even AMD 6900U struggles in many regards compared to M1 pro, and even more so at performance per watt. For example Cinebench runs at 118% more power draw on the Ryzen at only a 11% multi-core performance advantage.
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Qualcomm prioritizes cost over performance and it shows. Look at AMD for a performance comparison.
But doesn’t your statement prove that there are decisions and things the user of a node can make which effect the end result? Therefore, is not just process node that matters.
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Do we know whether that x86 backward compatibility is all that problematic? If I’m not mistaken, it is only used as a “public API” even in current CPUs, and on a microcode level it doesn’t have as much relevance.
For example: Decode. One of the things Apple CPUs keep being praised for is how wide they are. To be wide effectively and keep your execution units busy, you need a wide decoder. With aarch64 it is easy. Every instruction is 4 bytes on a 4 byte boundary. Want a 4-wide decoder? Ingest 16 bytes and copy-and-paste the same decoder 4 times. X86 instructions are variable-length: 1-15 bytes. And you do not know how long an…
What an x86 processor does is fetch an entire cacheline of instructions at once. Working out which byte corresponds to instructions is a straightforward state machine--and state machines can be parallelized as reduction tree, because function application is associative! (This is usually described as "x86 processors start decoding, in parallel, every byte as if it were the start of a new instruction.) My guess for x86 is that resolving instruction length takes a single cycle, a single stage of the instruction decode pipeline.
It's actually hard to come up with x86 instructions that are 15 bytes long. Your typical general-purpose instruction is going to max out around 4 bytes (REX + other prefix + opcode + ModR/M byte), and even that's a little long. A "complex" memory instruction that moves a 4-byte constant into a register + constant offset will manage 12 bytes, but that's really the limit of practical instruction. So there's no point building a decoder capable of ingesting that many extra-long instructions a cycle because it is so synthetic a use case.
Sure, you could design a better compressed ISA for decoding than x86, but the impact of its complexity on processors is vastly oversold. Just look at how much die space the x86 decoders actually take up to see how little of an impact it has.
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> Apple utterly dominates the mobile phone CPU landscape, That seems to be an interesting definition of "dominates". 14% of global smartphones from independents. 24% by Apple's claims. A curious kind of domination.
I'm sorry but I have to label this as a bad-faith attack. "dominates" in this context means being the fastest available, not necessarily that most people will buy that. It's like saying "the i9/Ryzen 7 dominates" and then answering with "most people buys Celerons/Athlons". You need to read the context of the conversation: it is about performance domination and not usershare domination.
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Qualcomm prioritizes cost over performance and it shows. Look at AMD for a performance comparison.
But doesn’t your statement prove that there are decisions and things the user of a node can make which effect the end result? Therefore, is not just process node that matters.