[deleted]
Intel's New Chimera: Alder Lake
91–100 of 253 posts
Re: Intel's New Chimera: Alder Lake
#92Earlier quoted context omitted.
I don’t completely agree. A MacBook Air M1 is 25% faster than a 10th generation Intel 10700K, running the same code full of floating point instructions and matrices. It’s not a simple matter of process node. The same MacBook Air can do hour long Skype video calls with ~9% charge consumption, with no discernible heat difference on the body too. M1 is a different beast.
Isn't M1 two process nodes ahead of the 10700K?
I'm not telling that process difference isn't the part of the picture, but the process difference is at most half of the story.
Working on HPC field and with generations and generations of Intel hardware, I can tell you that two node difference (alone) never gives you 25% real world performance in the realm of Intel, let alone theoretical.
Re: Intel's New Chimera: Alder Lake
#93Personally I don't really see a point in having a hybrid architecture like this unless it'll lead to massively increased core counts, and so far it doesn't look like it does. AMD still beats Intel in both core counts and power efficiency, and they're only using P cores so... what's the point of having E cores? But maybe that's just because it's a first generation technology for Intel? I hope things improve in the fut…
Does AMD beat Intel at power efficiency with varied or near-idle workloads, or just when running full-tilt?
Re: Intel's New Chimera: Alder Lake
#94Earlier quoted context omitted.
Indeed, I do sometimes wonder what it'd be like if they made the entire processor out of E cores.
the concept of “e-cores” is a rebranding of Atom. The Atom name is extremely tarnished from the days when it was super slow in-order netbook cores but Intel started seriously revamping the design in 2012-2014 with silvermont and airmont. They have been good for several years now - Goldmont (eg J5005) is between core2quad and Nehalem i5 (non-SMT) level performance despite running lower clocks (ie IPC is higher), and t…
In my analysis, only Gracemont (Atom 5th gen) is good and that’s for two reasons:
1. It has roughly the IPC of Skylake. 2. It’s the first Atom with AVX2. Even in 2021 Intel released brand new Atom cores without AVX2, which was introduced with Haswell (Haswell New Instructions). And in most tests, merely enabling AVX2 will yield 10% higher performance. That’s why Clear Linux has higher performance as they’re all tuned for Skylake. That’s also the reason why Red Hat couldn’t target x86-64-v3 with AVX2 for their new releases.
All previous Atom cores are slower than you imply:
Tremont (Atom 4th gen) has the IPC of Sandy Bridge. Goldmont (Atom 3rd gen) has the IPC of Core. It’s not exceeding Core like you imply. And Atom first gen is dog slow. It is like running a Pentium II/III CPU or a first generation Raspberry Pi. I find them an unsuccessful attempt of Intel of trying to create a mobile chip. In essence they just brought back a Pentium era chip.
This new Atom is fantastic though.
Re: Intel's New Chimera: Alder Lake
#95Personally I don't really see a point in having a hybrid architecture like this unless it'll lead to massively increased core counts, and so far it doesn't look like it does. AMD still beats Intel in both core counts and power efficiency, and they're only using P cores so... what's the point of having E cores? But maybe that's just because it's a first generation technology for Intel? I hope things improve in the fut…
AMD beats them because they are a process node ahead. Dunno why every comment implies there's some design gap that leads to M1 or AMD being more powerful or efficient. It's 90% the process node. There is no magic design sauce that makes those chips better. The big/little design change did seem to improve performance quite a bit for Intel, even using the same manufacturing node as before
There is a massive design gap between all Apple designed chips and non Apple designed chips. Apple’s chips are ridiculously humongous. They’re built for extremely wide, high performance applications for the past 10 years. A single A14 core can do 64 32-bit floating point operations in a single clock cycle. AMD/Intel were long at 16 operations and only the latest Intel went up to 32 operations.
Re: Intel's New Chimera: Alder Lake
#96Funny he defines Chimera as the mythical beast right at the start. I was sure he was thinking of the alternative definition:
> a thing that is hoped or wished for but in fact is illusory or impossible to achieve. "the economic sovereignty you claim to defend is a chimera"
That said Alder Lake does open up a bunch of new possibilities and isn't an illusion
Re: Intel's New Chimera: Alder Lake
#97You get a bunch of smart hardware guys into a room, they design this funky exotic architecture. Then the software goes "Allocate these threads to whatever is idle" and suddenly you've completely lost any possible advantage and are thrashing around with no idea what you're doing. The big-little architecture from Apple was accompanied by software that basically handles that for you. From what I heard there were similar…
I remember Mono, a .NET runtime, having to change its allocations to fit inside a smaller core. This was because a thread could start on a bigger core but then be shunted onto a smaller core. That fixed the crashing but obviously came with a loss of performance.
It was a bit more complicated than that: the issue was that one of the early big.LITTLE designs (Samsung's Exynos 8890) had different cacheline sizes on the big and little cores.
glibc's `__clear_cache` would cache the cacheline size on first call, so if the program was started on a big core then migrated onto a little core it would only flush every other cacheline. Which was an issue for any program needing to explicitely clear the caches, like most any JIT.
And the mitigation was not to "change its allocation", it was to bypass libgcc and handroll cache clearing: https://github.com/mono/mono/pull/3549
Source: https://www.mono-project.com/news/2016/09/12/arm64-icache/
This issue didn't only affect Mono e.g. dolphin (https://github.com/dolphin-emu/dolphin/pull/4204) and ppsspp (https://github.com/hrydgard/ppsspp/pull/8965) had been hitting the same issue and adopted mono's fix.
But fundamentally this is the 8890 being broken: as the Mono post notes, technically nothing precludes core migration in the middle of clearing the cache, which would also lead to broken behaviour, with no mitigation.
Re: Intel's New Chimera: Alder Lake
#98Earlier quoted context omitted.
I'm interested, what are you doing that can eat all those cores>
Anyone working on even a medium sized C++ project needs a very high end machine in order to compile. For large projects, 32 core work stations aren't crazy at all. Try building something like Firefox or Chromium on a quad core and you will see what I mean. The cost of the workstation is tiny compared to the cost of the engineer and you really don't want them to be waiting around for half their day (quite literally) b…
Compilation is largely memory bandwidth limited - some of the acceleration from cores might be that they have different memory channels rather than more CPUs.
M1 builds a lot faster than Intel CPUs even with fewer cores because of the memory bandwidth.
Re: Intel's New Chimera: Alder Lake
#99Earlier quoted context omitted.
Isn't M1 two process nodes ahead of the 10700K?
I'm not telling that process difference isn't the part of the picture, but the process difference is at most half of the story. Working on HPC field and with generations and generations of Intel hardware, I can tell you that two node difference (alone) never gives you 25% real world performance in the realm of Intel, let alone theoretical.
Even a single node difference can easily come close to a 25% increase in performance: "N5 technology provides about 20% faster speed than N7 technology or about 40% power reduction." [1]
Real world performance pretty much always lines up with these estimates. It's the main reason why we have exponential growth in computing power in the first place.
It would be a more fair comparison to compare the M1 to AMD's ZEN 4, which should be coming out next quarter.
[1] https://www.tsmc.com/english/dedicatedFoundry/technology/log...
Re: Intel's New Chimera: Alder Lake
#100Earlier quoted context omitted.
the concept of “e-cores” is a rebranding of Atom. The Atom name is extremely tarnished from the days when it was super slow in-order netbook cores but Intel started seriously revamping the design in 2012-2014 with silvermont and airmont. They have been good for several years now - Goldmont (eg J5005) is between core2quad and Nehalem i5 (non-SMT) level performance despite running lower clocks (ie IPC is higher), and t…
As an aside, I don't think even the early Atom processors were as terrible as their reputation branded them. I had an early Atom-based netbook, and it was totally acceptable... if running Linux (or XP). Kind of like the "Vista debacle", I think Atoms were just unsuited to running Windows 7. Maybe I'm too forgiving or forgetful, but I used that netbook for many years, and it wasn't that slow with Linux. (7 was pretty…
I had an eeepc 901, used it for years with linux. First it ran gnome 2 I think, then xfce. Perfectly useful little machine. In later years I switched to lxde to eke a little more out of a little less.
In that form factor, and costing what it did, I was massively impressed.