Ask HN: Asynchronous FPGAs and flowchart programming • Hacker News Board

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#31

Post by auxym » Fri, May 13, 2022, 1:10 PM UTC

Labview provides a dataflow programming environment that can be used to program FPGAs (eg in the compactRIO line of hardware).

Not saying it's great (it's not), but it works in its niche: programming of one-off test fixtures by people who really have no idea about programming, digital circuits or FPGAs but might need the performance they afford (eg real-time high frequency control of a 100K+ RPM prototype gas turbine). You also have to be willing to shell out for their hardware (and labview itself), but in the testing world, I've found their hardware to actually be on the "pretty affordable for what you get" side, compared to the likes of HBM eDAQ or Siemens LMS setups.

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#32

Post by keikobadthebad » Fri, May 13, 2022, 2:04 PM UTC

thesz wrote: post #22

keikobadthebad wrote: post #7

Earlier quoted context omitted.

"Way more efficient" as a conceptual and implementation model. But synchronous logic always leaves some speed on the table, since you have to choose the global clock rate for the longest data path that must complete in one clock; for any given path that may be active on a clock, it's likely to not be the longest. In practice it's possible to architect synchronous critical paths with pipelining to keep the worst singl…

You forgot that clock delay is computed for worst-case register and combinational logic behavior, e.g., "99.9999% of all registers need this amount of time for signal to be stable before write", "99.9999% of this gate in real silicon will have this delay". The chart I saw several years ago put about half of typical clock cycle delay into this "reserve time" part. I guess things did not change much since then.

It depends what you are doing but with async it's possible to synthesize SR latches that don't have these setup / hold and metastability problems, the output of the logic is directly strobes that set or reset the storage element.

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#33

Post by JaCaLet » Fri, May 13, 2022, 2:28 PM UTC

balsam wrote: post #30

hutzlibu wrote: post #23

"I interned at You Know Solutions and learned the flowchart programming environment they use. " And what do they use? How does it work, do you click your flowcharts together?

Their patent seem to mention flowcharts: https://www.freepatentsonline.com/9003383.html

Yup the flowcharts are the key to the parallelizing of code

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#34

Post by JaCaLet » Fri, May 13, 2022, 2:30 PM UTC

hutzlibu wrote: post #23

"I interned at You Know Solutions and learned the flowchart programming environment they use. " And what do they use? How does it work, do you click your flowcharts together?

It’s similar to ladder logic. It’s called FlowPro. You can combine flowcharts together that’s easy.

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#35

Post by atomicflow » Fri, May 13, 2022, 2:50 PM UTC

balsam wrote: post #30

hutzlibu wrote: post #23

"I interned at You Know Solutions and learned the flowchart programming environment they use. " And what do they use? How does it work, do you click your flowcharts together?

Their patent seem to mention flowcharts: https://www.freepatentsonline.com/9003383.html

I am familiar with the you know solutions patents and the one you refer to is for parallelizing C code and other languages into the flowcharts. Here is a link to the asynchronous design patent called "processing circuits for parallel asynchronous modeling and execution". https://www.freepatentsonline.com/10181003.html

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#36

Post by atomicflow » Fri, May 13, 2022, 2:57 PM UTC

JaCaLet wrote: post #34

hutzlibu wrote: post #23

"I interned at You Know Solutions and learned the flowchart programming environment they use. " And what do they use? How does it work, do you click your flowcharts together?

It’s similar to ladder logic. It’s called FlowPro. You can combine flowcharts together that’s easy.

It's not really similar to ladder logic but in those days it did the same thing, controlled machines. In ladder logic all of the rungs of the ladder are evaluated all of the time but with flowcharts only the necessary part of each flowchart is executed as the machine cycles.

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#37

Post by atomicflow » Fri, May 13, 2022, 3:10 PM UTC

miga wrote: post #24

Looks like you want to implement "asynchronous circuit": https://en.wikipedia.org/wiki/Asynchronous_circuit These basically need a handshaking logic for every independent data path.

Take a look at the you know solutions patent. It doesn't use handshaking and the design can be clockless. https://www.freepatentsonline.com/10181003.html

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#38

Post by JaCaLet » Fri, May 13, 2022, 3:14 PM UTC

tkanarsky wrote: post #4

FPGA is literally as parallel as you can make a computation, the ultimate jaunt towards the space end of the time/space tradeoff. Don't like waiting two cycles for your ALU to finish working on previous data? Put another ALU right next to it. So yes, you can totally make a parallel program on an FPGA. As long as there isn't a data or control dependency between two statements, they can be implemented to execute simult…

The flowchart programming is built to be parallel. It’s inherent to the ordering of execution.

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#39

Post by hutzlibu » Fri, May 13, 2022, 3:15 PM UTC

atomicflow wrote: post #35

balsam wrote: post #30

Earlier quoted context omitted.

Their patent seem to mention flowcharts: https://www.freepatentsonline.com/9003383.html

I am familiar with the you know solutions patents and the one you refer to is for parallelizing C code and other languages into the flowcharts. Here is a link to the asynchronous design patent called "processing circuits for parallel asynchronous modeling and execution". https://www.freepatentsonline.com/10181003.html

Interesting, but not great, since I work on something related and I was not aware of any patents in that area. But it should be distinct enough, I hope. (I don't target FPGAs for example, but I have zero experience with patents, so lets see how that works out)

Re: Ask HN: Asynchronous FPGAs and flowchart programming

#40

Post by JaCaLet » Fri, May 13, 2022, 3:37 PM UTC

ajb wrote: post #25

Not sure if you are actually talking about clockless logic. Maybe you are talking about asynchrony at a higher level of granularity. But in fact there was a company founded to make FPGAs based on clockless logic: Achronix. They found that their customers wanted to map clocked designes onto their FPGAs and don't make any noise about clockless anymore - possibly their designs still use it under the hood, possibly not.

Yes clockless logic no handshaking