Earlier quoted context omitted.
Decode doesn't take up much space in a high-end processor. Even if your architecture's decoder doesn't "scale" as well, you can just throw a bunch more transistors at it to get performance. That said, I doubt there's many CPU designers unhappy about a simpler ISA...
If macro op fusion is viable then there are more opportunities to throw more transistors at it to get more performance.
India reveals RISC-V CPU roadmap, expects product by 2023
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Re: India reveals RISC-V CPU roadmap, expects product by 2023
#42Hopefully they'll take a holistic approach - from processor to memory to disk to kernel to application. India should have players in every aspect of technology. They should also invest more in research. Why does india have less supercomputers than sweden? Does this mean that india is doing less research in some aspects than a country of just 10 million people? https://en.wikipedia.org/wiki/TOP500 India is not and has…
Which do you prioritise, lifting people out of poverty/squalid living conditions, research, industrial expansion, power projection (aircraft carriers so that India can protect it's interests, live up to it's potential, counter Chinese expansion), etc. ? There's a decent argument to be made that just encouraging and investing in industry and research will increase incomes and improve living conditions but it's unlikely to be sufficient.
Re: India reveals RISC-V CPU roadmap, expects product by 2023
#43Re: India reveals RISC-V CPU roadmap, expects product by 2023
#44IIRC the Shakti family didn't include the C extension, which would make it incompatible with most Linux distros who have chosen to require it. Is this still the case?
Re: India reveals RISC-V CPU roadmap, expects product by 2023
#45Re: India reveals RISC-V CPU roadmap, expects product by 2023
#46Once a working computer is available commercially, A mandate would be issued by the central government ministries to 250+ Public Sector Undertaking ( Companies with >50% govt equity) to procure only these RISCV computers. This way we can definitely bring it up to speed real fast. PS: From my experience working currently for one of those PSUs .
I doubt this will happen, even if they do issue a mandate. Indian government computers are still running windows 7 or so and its hard to get them to switch to Linux. What happens when theyre forced to run Linux and a new architecture ? All of them will just obtain exemptions to continue using windows + x86 claiming some software they need doesnt work. Teaching a 50 year govt employee how to use QEMU + Wine to emulate…
Re: India reveals RISC-V CPU roadmap, expects product by 2023
#47Earlier quoted context omitted.
If macro op fusion is viable then there are more opportunities to throw more transistors at it to get more performance.
It's not yet clear if macro-op fusion will really be a thing.
Re: India reveals RISC-V CPU roadmap, expects product by 2023
#48IIRC the Shakti family didn't include the C extension, which would make it incompatible with most Linux distros who have chosen to require it. Is this still the case?
Probably someone will read your comment and think "the C extension" means "support for the programming language C", but that is not the case. Standard RISC-V instruction set extensions are identified by letters: M for multiply (and unfortunately divide), F for floating point, D for double-precision floating point, A for atomic memory operations (necessary for SMP), V for vector operations, and so on.
The C extension is the "compressed" extension, which represents the most common instructions in 16 bits instead of the usual 32. Without the C extension, RISC-V code is relatively bulky, which is a disadvantage not only for limited-memory microcontrollers but also because, if you have an instruction cache, less code fits into it, so most software runs slower. With the C extension, RISC-V code density is at least competitive with the best alternatives like Thumb2, and in most cases slightly better. This is particularly interesting in the 64-bit space, because arm64 (aarch64) has abandoned the Thumb2-style compressed instruction approach.
Re: India reveals RISC-V CPU roadmap, expects product by 2023
#49Quoted post unavailable.
It's a modern website in brutalist web style. Looks perfect.
Apparently the Ministry of Electronics & IT is headed by the government officials who hired the people who approved this press release. I hope the involvement of such people does not destroy the Shakti project, which is one of the most promising 1% of RISC-V implementations.
Re: India reveals RISC-V CPU roadmap, expects product by 2023
#50India, with its stable democracy is a safer bet for the world as a source of chips.