So is UCI-e a competitor/potential successor for something like Intel's QPI (or whatever they are using now)?
Single-chip processors have reached their limits
61–70 of 159 posts
Re: Single-chip processors have reached their limits
#62I hope we are going to get back to a more asymmetric multi-processing arrangement in the near term where we abandon the fiction of a processor or two running the whole show with peripheral systems that have as little smarts as possible and promote them to at least second class citizens. These systems are much more powerful than when these abstractions were laid down, and at this point it feels like the difference bet…
That kind of exists since most I/O devices have CPU cores in them, although usually hidden behind register-based interfaces. Apple has taken it a little further by using the same core everywhere and creating a standard IPC mechanism.
Re: Single-chip processors have reached their limits
#63The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…
... that's the exact opposite of every economic and yield advantage that chiplet design addresses, isn't it?
Want to fine tune your chip offering to some multiple of 8 cores (arbitrary example of the # cores on the chiplet)? Just a packaging issue.
Want to upbin very large corecounts that generally overclock quite well? For a massive unichip described, maybe there are sections of the chip that are clocking well and sections that aren't: you're stuck. With chiplets, you have better binning granularity and packaging.
Want to fine-tune various cache levels? I believe from what I've read that AMD is doing L3 on a separate chiplet (and vertically stacking it!). So you can custom-tune the cache size for chip designs,
You can custom-process different parts of the "CPU" with different processes and fabrication, possibly even different fab vendors.
You can upgrade various things like memory support and other evolving things in an isolated package, which should help design and testing.
The interconnects are the main problem. But then again, I can't imaging what a foot-wide CPU introduces for intra-chip communication, it probably would have it's own pseudo-interconnect highway anyway.
Maybe you don't even need to reengineer some chiplets between processor generations. If the BFD of your new release is some improvement to the higher or lower cpus in the High-Low designs, but the other is the same, then that should be more organizational efficiency.
Intel and others have effectively moved from gigantic integrated circuits decades ago: motherboard chipsets were always done with a separate cheaper fab that was a gen or two behind the CPU.
Maybe when process tech has finally stabilized for a generation now that process technology seems to be stagnating more, then massive wafer designs will start to edge out chiplet designs, but right now it appears that the opposite has happened and will continue for the foreseeable future.
Re: Single-chip processors have reached their limits
#64I'm embarrassed to admit I still don't quite understand what a chiplet is, would be very grateful for your input here. If a thread can run on multiple chiplets then this is awesome and seems like a solution. If one thread == one chiplet, then*: - a chiplet is equivalent to a core, except with speedier connections to other cores? - this isn't a solution, we're 15 years into cores and single-threaded performance is sti…
AMD Epyc is (AFAIK) what popularized the term. Their current design has a memory controller (PCIe controller, 8 x 64 bit channels of ram, etc) and 8 chiplets which are pretty much just 8 cores and a infinity fabric connection for a cache coherent connection to other CPUs (in the same or other sockets) and dram.
So generally Epyc come with some multiple of 8 CPUs enabled (1 per chiplet) and the latency between cores on the same chiplet is lower than the latency to other chiplets.
This allows AMD to target high end servers (up to 64 cores), low end (down to 16), workstations with threadripper (4 chiplets instead of 8), and high end desktops (2 chiplets instead of 8) with the same silicon. This allows them to spend less on fabs, R&D, etc because they can amortize the silicon over more products/volume. It also lets them bin them so chiplets with bad cores can still be sold. It's one of the things that lets AMD compete with the much larger volume Intel has, and do pretty well against numerous silicon designs Intel chips.
Re: Single-chip processors have reached their limits
#65The best chiplet interconnect may turn out to be no interconnect at all. Wafer scale integration [1] has come up periodically over the years. In short, just make a physically larger integrated circuit, potentially as large as the entire wafer -- like a foot across. As I understand it, there's no particular technical hurdle, and indeed the progress with self-healing and self-testing designs with redundancy to improve…
Sounds like a great development if it works out. But consider also that you can stick chiplets on top of each other vertically. That means you can put chiplets much closer together than if they were constrained to exist on the same single plane of the wafer. Now how about stacking wafers on top of wafers? That could be super, but there might be technical difficulties, which maybe sooner or later can be overcome.
> But consider also that you can stick chiplets on top of each other vertically.
The problem there is heat dissipation. Already the performance constraint on consumer chips like the Apple M1 is how well it can dissipate heat in the product it's placed in (see Macbook Air vs Mac Mini). Stacking the chips just makes it worse.
Re: Single-chip processors have reached their limits
#66I hope somebody with relevant knowledge can answer this question, please: what % of the costs is "physical cost per unit" and what % is maintaining the I+D, factories, channels...?
In other words, if a chip with 100x size (100x gates, etc.) made sense, would it cost 100x to produce or just 10x or just 2x?
Edit: providing there wouldn't be additional design costs, just stacking current tech.
Re: Single-chip processors have reached their limits
#67Despite the limitations apparently present in single chip/CPU systems, they can still provide an insane amount of performance if used properly.
There are also many problems that are literally impossible to make faster or more correct than by simply running them on a single thread/processor/core/etc. There always will be forever and ever. This is not a "we lack the innovation" problem. It's an information-theoretic / causality problem you can demonstrate with actual math & physics. Does a future event's processing circumstances maybe depend on all events received up until now? If yes, congratulations. You now have a total ordering problem just like pretty much everyone else. Yes, you can cheat and say "well these pieces here and here dont have a hard dependency on each other", but its incredibly hard to get this shit right if you decide to go down that path.
The most fundamental demon present in any distributed system is latency. The difference between L1 and a network hop in the same datacenter can add up very quickly.
Again, for many classes of problems, there is simply no handwaving this away. You either wait the requisite # of microseconds for the synchronous ack to come back, or you hope your business doesnt care if john doe gets duplicated a few times in the database on a totally random basis.
Re: Single-chip processors have reached their limits
#68I hope somebody with relevant knowledge can answer this question, please: what % of the costs is "physical cost per unit" and what % is maintaining the I+D, factories, channels...? In other words, if a chip with 100x size (100x gates, etc.) made sense, would it cost 100x to produce or just 10x or just 2x? Edit: providing there wouldn't be additional design costs, just stacking current tech.
There's many limiting factors... one is the reticle limit.
But most fundamental is the defect density on wafers. If you have, say, 10 defects per wafer, and you have 1000 chips on it: odds are you get 990 good chips.
If you have 10 chips on the wafer, you get 2-3 good chips per wafer.
Of course, there's yield maximization strategies, like being able to turn off portions of the die if it's defective (for certain kinds of defects).
For the upper limit, look at what Cerebras is doing with wafer scale. Then you get into related, crazy problems, like getting thousands of amperes into the circuit and cooling it.
Re: Single-chip processors have reached their limits
#69I hope somebody with relevant knowledge can answer this question, please: what % of the costs is "physical cost per unit" and what % is maintaining the I+D, factories, channels...? In other words, if a chip with 100x size (100x gates, etc.) made sense, would it cost 100x to produce or just 10x or just 2x? Edit: providing there wouldn't be additional design costs, just stacking current tech.
I'm not an expert, or even an amateur, here but I defects are inevitable. So if you _need_ 100x the size without defects and one defect ruins the chip the cost might be 10000x to produce
Re: Single-chip processors have reached their limits
#70Earlier quoted context omitted.
You're implying you can't put big powerful cores on chiplets but that's not true at all.
Hardly - performance/core hasn’t flatlined, but has not maintained the same growth over time (decades) in performance we’ve traditionally had. That’s the problem. So if you want better aggregate performance, more cores has been the plan for a decade+ now. FLOP/s per core or whatever other metric you choose to use. Previously it was possible to get 20-50% or more performance improvements even year to year for a core.
I wasn't talking about improvement at all. This was about big strong cores versus efficient cores, which is a tradeoff that always exists.
You could choose between 20 strong cores or 48 efficient cores on the same die space across four chiplets, for example.