Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

Ask HN: How does a CPU communicate with a GPU?

news.ycombinator.com

Post reply on HN
Print view View original

51–60 of 100 posts

Re: Ask HN: How does a CPU communicate with a GPU?

#51

Post by simne »

tenebrisalietum wrote: post #43
divbzero wrote: post #7

Earlier quoted context omitted.

Going one deeper, how does the communication work on a physical level? I’m guessing the wires of the PCI Express bus passively propagate the voltage and the CPU and GPU do “something” with that voltage?

Older CPUs - the CPU had a bunch of A pins (address), a bunch of D pins (data). The A pins would be a binary representation of an address, and the D pins would be the binary representation of data. A couple of other pins would select behavior (read or write) and allow handshaking. Those pins were connected to everything else that needed to talk with the CPU on a physical level, such as RAM, I/O devices, and connector…

> Older CPUs - the CPU had a bunch of A pins (address), a bunch of D pins (data).

And on some buses, some or all A/D pins where multiplexed, so transaction divided to address set part and data read/write part.

Re: Ask HN: How does a CPU communicate with a GPU?

#52

Post by copperx »

vletal wrote: post #30
Keyframe wrote: post #27

Earlier quoted context omitted.

If OP or anyone else wants to see this firsthand.. well shit, I feel old now, but.. try an exercise into assembly programming of commodore 64. Get a VICE emulator and dig into it for a few weeks. It's real easy to get into, CPU (6502 based), video chip (VIC II), sound chip (famous SID), ROM chips.. they all love in this address space (yeah, not mentioning pages), CPU has three registers.. it's also real fun to get in…

Nice exercise. Similarly I learned most about basic computer architecture by programing 8050 in ASM as well as C. And I'm 32. Am I old yet? I'm not right? Right?

> Am I old yet? I'm not right? Right?

Yes, but being old isn't bad. I, for one, long for the day when I'll be unable to produce and contribute to society.

Re: Ask HN: How does a CPU communicate with a GPU?

#53

Post by pedrolins »

pizza234 wrote: post #28

You'll find a very good introduction in the comparch book "Write Great Code, Volume 1", chapter 12 ("Input and Output"), which also explains the history of system buses (therefore, you'll find an explanation of how ISA works). Interestingly, there is a footnote explaining that "Computer Architecture: A Quantitative Approach provided a good chapter on I/O devices and buses; sadly, as it covered very old peripheral dev…

Wow. Just skimmed across that chapter and that looks like a great resource. No wonder I couldn't find it in any of my searching sessions, I'd never think a book titled like that would cover hardware concepts so extensively. This will definitely help me in understanding buses better. Thank you.

Re: Ask HN: How does a CPU communicate with a GPU?

#54

Post by mikehollinger »

divbzero wrote: post #7
rayiner wrote: post #3

Typically CPU and GPU communicate over the PCI Express bus. (It’s not technically a bus but a point to point connection.) From the perspective of software running on the CPU, these days, that communication is typically in the form of memory-mapped IO. The GPU has registers and memory mapped into the CPU address space using PCIE. A write to a particular address generates a message on the PCIE bus that’s received by th…

Going one deeper, how does the communication work on a physical level? I’m guessing the wires of the PCI Express bus passively propagate the voltage and the CPU and GPU do “something” with that voltage?

Oh! I know this one! PCI itself is comprised of several layers, from a physical layer, to a link layer, to a transaction layer and application layers.

At the physical level we're literally pushing the limits of semiconductor physics as an industry. :-) There's all sorts of tricks, like 8b10b encodings[1] to address error handling and recovery, and then different ways to itself transmit the PCI signal. You can, for example, encode a PCIe signal on an optical cable. :-) The bus itself is divided into "lanes" which can be aggregated into various "widths" - so you'll see x1, x4, x8, x16 etc. This compounds the problem, in that each lane is negotiated. See this video[2] for what appears to be a nice overview. I haven't watched the video in depth, but clicking around, this seems reasonable to get a sense of what's what.

There's a good reference on the rest of the protocol here: https://www.mindshare.com/files/ebooks/pci%20express%20syste... . Put bluntly - it's amazing that anything works at all, technology is as cheap as it is, ubiquitous as it is, and continues to get cheaper, and more powerful on a daily basis.

If you want your mind blown - look up how modern WiFi works, and what we take for granted today. Beam forming. [3] 256-QAM encoding.[4]

Source: I wrote firmware for very, very large servers at one point in my career. Code that I wrote still (AFAIK) is still running, and writing a a 32-bit test pattern into a register once every second to validate that a particular chip is working ok. That test pattern? 0x4D494B45, which is "MIKE" in ASCII. :-)

Math (and science) is amazing. :-)

[1] https://en.wikipedia.org/wiki/8b/10b_encoding

[2] https://www.youtube.com/watch?v=EHkuzkNWXFk

[3] https://www.youtube.com/watch?v=xGkyZw98Tug

[4] https://www.minim.com/blog/what-is-qam

Re: Ask HN: How does a CPU communicate with a GPU?

#55

Post by pedrolins »

brooksbp wrote: post #38

Woah there, my dude. Let's try to understand a simple model first. A CPU can access memory. When a CPU performs loads & stores it initiates transactions containing the address of the memory. Therefore, it is a bus master--it initiates transactions. A slave accepts transactions and services them. The interconnect routes those transactions to the appropriate hardware, e.g. the DDR controller, based on the system addres…

Yeah, your explanation really hits the nail in regards to what I was trying to understand - MMIO coupled with all of that bus dynamic of a master and slave going on. It's clear to me now that my knowledge gap resides in not knowing enough about interconnects. Thanks a lot!

I do wonder, why aren't interconnects more emphasized in the courses I took? All I've seen was just oversimplified pictures of the process. Your explanation goes just enough into the lower-level aspects of the process to allow me to piece it.

Re: Ask HN: How does a CPU communicate with a GPU?

#56

Post by pedrolins »

dragontamer wrote: post #21

I'm no expert on PCIe, but its been described to me as a network. PCIe has switches, addresses, and so forth. Very much like IP-addresses, except PCIe operates on a significantly faster level. At its lowest-level, PCIe x1 is a single "lane", a singular stream of zeros-and-ones (with various framing / error correction on top). PCIe x2, x4, x8, and x16 are simply 2x, 4x, 8x, or 16 lanes running in parallel and independ…

Yeah, as I've read other responses to my post I've been able to better define my difficulties in understanding CPU-GPU communication. I was having a hard time separating the MMIO concept from the communications protocol that ties together all of these devices (based on what you've explained that'd be PCIe). I actually haven't learned about PCIe as of yet, so the way you've introduced the concept has set me up to further look into it, thanks.

Re: Ask HN: How does a CPU communicate with a GPU?

#57

Post by pedrolins »

arduinomancer wrote: post #22
throwmeariver1 wrote: post #11

Everyone in tech should read the book "Understanding the Digital World" by Brian W. Kernighan.

Is it very in-depth or more for layman readers?

It doesn't really answer my question, but from what I've seen in the TOC I'd say it's equivalent to an introductory course on computer architecture + computer systems and some cryptography as well. Kind of an introduction (don't get me wrong with the word 'introduction', it covers a decent amount of material) to the most important concepts and technologies that guide computers and the internet.

Re: Ask HN: How does a CPU communicate with a GPU?

#58

Post by pedrolins »

justsomehnguy wrote: post #23

TL;DR: bi-directional memory access with some means to notify the other part about "something has changed". It's not that different for any other PIC/E device, be it a network card or a disk/HBA/RAID controller. If you want to understand how it came to this - look at the history of ISA, PCI/PCI-X, a short stint for AGP and finally PCI-E. Other comments provides a good ELI15 for the topic. A minor note about "bus" - f…

I find it very interesting that you mention looking at the history of ISA's first in order to understand the current iteration of the technology.

I was reading the RISC-V privileged ISA recently and the amount of seemingly arbitrary registers and behaviours that must be implemented to support a UNIX-like OS is crazy, and that got me thinking about the history behind all of these things that the hardware must support in order to support the OS.

But thank you for the pointers, I'll definitely use this.

Re: Ask HN: How does a CPU communicate with a GPU?

#59

Post by phendrenad2 »

At a high level, it's actually really simple. Your PCIe devices are each given a region of the address space, say, 0x8428000000000000-0x8428000000000fff. Just write to that region from kernel mode. But what do you write? Well, that isn't standardized. It's not even really documented. The best documentation is the source code to the GPU drivers in the Linux kernel, which are usually added to by engineers working at GPU vendors, and they don't discuss it much.

Re: Ask HN: How does a CPU communicate with a GPU?

#60

Post by phendrenad2 »

pedrolins wrote: post #58
justsomehnguy wrote: post #23

TL;DR: bi-directional memory access with some means to notify the other part about "something has changed". It's not that different for any other PIC/E device, be it a network card or a disk/HBA/RAID controller. If you want to understand how it came to this - look at the history of ISA, PCI/PCI-X, a short stint for AGP and finally PCI-E. Other comments provides a good ELI15 for the topic. A minor note about "bus" - f…

I find it very interesting that you mention looking at the history of ISA's first in order to understand the current iteration of the technology. I was reading the RISC-V privileged ISA recently and the amount of seemingly arbitrary registers and behaviours that must be implemented to support a UNIX-like OS is crazy, and that got me thinking about the history behind all of these things that the hardware must support…

Not that ISA: :) https://en.wikipedia.org/wiki/Industry_Standard_Architecture
Post reply on HN