Ask HN: How does a CPU communicate with a GPU?

Is my understanding correct that compared to those historical architectures, modern GPUs are a lot more asynchronous?

What I mean that these days you'd issue a data transfer or program execution on the GPU, they will complete at its own pace and the CPU in the meanwhile continues executing other code; in contrast in those 8 bitters you'd poke a video register or whatev and expect that to have more immediate effect allowing those famous race the beam effects etc?

There's a nice guide by Ben Eater on Youtube about a breadboard computers: https://www.youtube.com/playlist?list=PLowKtXNTBypFbtuVMUVXN...

It doesn't sport any modern features like DMA, but builds up from the core basics: a 6502 chip, a clock, and a blinking LED, all hooked up on a breadboard. He also built a basic VGA card and explains protocols like PS/2, USB, and SPI. It's a great introduction or refresher into the low level hardware concepts behind computers. You can even buy kits to play along at home!

I agree that PCIe is mostly shared memory system.

But for videocards this sharing is unequal, because their RAM sizes exceeds 32bit address space, and lot of still used mainboards have 32bit PCIe controller, so all PCIe addresses should be inside 4GB address space, and this is seen on windows machines as total installed memory is nor all, but minus approximately 0.5GB, from which 256MB is videoram access window.

So in most cases, remain in force rule, that videocard share all it's memory through 256mb window using bank-switching.

As for GPU read main system memory, usually this is useless, because vram is magnitudes faster, even if not consider usage of bus bandwidth by other devices, like HDD/SSD.

And in most cases, only usage of access GPU to main system memory, is traditional read of textures (for 3D accelerator) from main system memory - for example ALL 3D software using GPU rendering, could only use for this videoram, none use system ram.

Woah there, my dude. Let's try to understand a simple model first.

A CPU can access memory. When a CPU performs loads & stores it initiates transactions containing the address of the memory. Therefore, it is a bus master--it initiates transactions. A slave accepts transactions and services them. The interconnect routes those transactions to the appropriate hardware, e.g. the DDR controller, based on the system address map.

Let's add a CPU, interconnect, and 2GB of DRAM memory:

  +-------+
  |  CPU  |
  +---m---+
      |
  +---s--------------------+
  |      Interconnect      |
  +-------m----------------+
          |
     +----s-----------+
     | DDR controller |
     +----------------+
  
  
  System Address Map:
  
    0x8000_0000 - 0x0000_0000  DDR controller

So, a memory access to 0x0004_0000 is going to DRAM memory storage.

Let's add a GPU.

  +-------+    +-------+
  |  CPU  |    |  GPU  |
  +---m---+    +---s---+
      |            |
  +---s------------m-------+
  |      Interconnect      |
  +-------m----------------+
          |
     +----s-----------+
     | DDR controller |
     +----------------+
  
  
  System Address Map:
  
    0x9000_0000 - 0x8000_0000  GPU
    0x8000_0000 - 0x0000_0000  DDR controller

Now the CPU can perform loads & stores from/to the GPU. The CPU can read/write registers in the GPU. But that's only one-way communication. Let's make the GPU a bus master as well:

  +-------+    +-------+
  |  CPU  |    |  GPU  |
  +---m---+    +--s-m--+
      |           | |
  +---s-----------m-s-----+
  |      Interconnect      |
  +-------m----------------+
          |
     +----s-----------+
     | DDR controller |
     +----------------+
  
  
  System Address Map:
  
    0x9000_0000 - 0x8000_0000  GPU
    0x8000_0000 - 0x0000_0000  DDR controller

Now, the GPU can not only receive transactions, but it can also initiate transactions. Which also means it has access to DRAM memory too.

But this is still only one-way communication (CPU->GPU). How can the GPU communicate to the CPU? Well, both have access to DRAM memory. The CPU can store information in DRAM memory (0x8000_0000 - 0x0000_0000) and then write to a register in the GPU (0x9000_0000 - 0x8000_0000) to inform the GPU that the information is ready. The GPU then reads that information from DRAM memory. In the other direction, the GPU can store information in DRAM memory, and then send an interrupt to the CPU to inform the CPU that the information is ready. The CPU then reads that information from DRAM memory. An alternative to using interrupts is to have the CPU poll. The GPU stores information in DRAM memory and then sets some bit in DRAM memory. The CPU polls on this bit in DRAM memory, and when it changes, the CPU knows that it can read the information in DRAM memory that was previously written by the GPU.

Hope this helps. It's very fun stuff!

It might be easier to start with older or simpler/slower buses. ISA, SPI, I2C. In some ways ISA is very different - latching multiple parallel channels together instead of ganging independent serial lanes. But it makes sense to start off simple and consider the evolution. Modern PCIe layers several awesome technologies together, especially FEC. Originally they used 8b10b but I see now they're using 242b256b.