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Verilog Is Weird

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Re: Verilog Is Weird

#111

Post by shadowgovt »

jwilk wrote: post #107
shadowgovt wrote: post #94

Earlier quoted context omitted.

And hugo is technically correct (the best kind of correct) in that parens are in the sub-delims reserved set of characters for HTML ( https://www.ietf.org/rfc/rfc3986.txt section 2.2), and since they're being used in a context where the enclosing language considers parens to have special meaning, they should be octet-encoded in the hugo file. (In practice, my experience with hugo is that it will generally get them ri…

On the contrary, because parentheses are reserved, percent-encoding them is not necessarily safe: > Percent-encoding a reserved character, or decoding a percent-encoded octet that corresponds to a reserved character, will change how the URI is interpreted by most applications. https://datatracker.ietf.org/doc/html/rfc3986#section-2.2

That is, unfortunately, one of those chunks of English that is hard to interpret.

"Safe" here isn't really what the RFC is talking about; the RFC is saying that if you take a URI and add or remove percent encoding for those characters, you might change the way that the URI is interpreted (because those characters mean something in the enclosing context). In other words, you can't encode or decode them without risking a change to the interpretation, but whether encoding or decoding is "safe" is going to be context-specific (broadly speaking, the safest thing to do is to encode them and leave them encoded).

Re: Verilog Is Weird

#112

Post by magicalhippo »

Taniwha wrote: post #93
jstanley wrote: post #32

Earlier quoted context omitted.

> "always X" just means loop waiting for X I think this is actually not right. There's not any kind of loop that is running, it's triggered by signal edges. That's the fundamental difference between hardware and software that makes hardware difficult for software people. Everything happens simultaneously.

A little background - I've written a couple of Verilog compilers - you can have always statements with multiple events, protocol state machines a bit like: always @(posedge clk) begin do some stuff if (condition) begin @(posedge clk); do some more stuff end else begin @(posedge clk); do some different stuff end ...... end Synopsis will happily synthesise this, generating the implied state variable. There really is a…

But if the result is a flipflop, where is the loop?

Re: Verilog Is Weird

#113

Post by jiggawatts »

rowanG077 wrote: post #109
jiggawatts wrote: post #105

Earlier quoted context omitted.

That function example is not allowed in Haskell. It's pure functional throughout , not just at "function boundaries". I agree that conceptually a language can be made where only function boundaries are required to be side-effect free, and internally "anything goes" as long as it doesn't pollute the outside world. This might be a good model for circuit design, especially if using something like an IO monad to store pe…

Such a function is perfectly allowed and even encouraged, see here where I allocate a mutable array with undefined values and write and read from it in a pure function. Basically replicating the pseudo imperative code I have written before: https://replit.com/@RowanGoemans/QuarrelsomeUtilizedMicroker... Using mutable vectors like this is a must if you need to write high performance Haskell code. I have also written c…

That's a clever hack that was added decades after I learned Haskell.

I mean... it works, but it's not in the spirit of Haskell, which is my point.

It's not impossible to write pure functional software in C. It just goes against its grain.

Re: Verilog Is Weird

#114

Post by rowanG077 »

jiggawatts wrote: post #113
rowanG077 wrote: post #109

Earlier quoted context omitted.

Such a function is perfectly allowed and even encouraged, see here where I allocate a mutable array with undefined values and write and read from it in a pure function. Basically replicating the pseudo imperative code I have written before: https://replit.com/@RowanGoemans/QuarrelsomeUtilizedMicroker... Using mutable vectors like this is a must if you need to write high performance Haskell code. I have also written c…

That's a clever hack that was added decades after I learned Haskell. I mean... it works , but it's not in the spirit of Haskell, which is my point. It's not impossible to write pure functional software in C. It just goes against its grain.

Monadic computations are very much in the spirit of Haskell. I don't think the Haskell community view the ST monad as a hack. It's one of many tools in the box of any Haskell programmer.

Re: Verilog Is Weird

#115

Post by Taniwha »

magicalhippo wrote: post #112
Taniwha wrote: post #93

Earlier quoted context omitted.

A little background - I've written a couple of Verilog compilers - you can have always statements with multiple events, protocol state machines a bit like: always @(posedge clk) begin do some stuff if (condition) begin @(posedge clk); do some more stuff end else begin @(posedge clk); do some different stuff end ...... end Synopsis will happily synthesise this, generating the implied state variable. There really is a…

But if the result is a flipflop, where is the loop?

Always implies an outer loop, when you reach the bottom of the loop you go back to the top and do the original event wait again, but not until you've waited for the intermediate event waits

In simulation this is easy to implement, but in synthesis the synthesis tool needs to rewrite it as some hidden flops for state and a top level case statement

Re: Verilog Is Weird

#116

Post by fargle »

pjc50 wrote: post #31
Taniwha wrote: post #24

I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or what…

> Once you have that stuff in your head you can turn to verilog (or vhdl or whatever) and learn how to map these ideas into the language Yes, and per the other comment this is a huge limitation of them - you don't have Javascript authors saying "you need to work out what you want in this other paradigm and then translate it". You occasionally see people writing C this way though, by working out what they want from th…

This article is really dated (2013?). Since it was written "Verilog" is now merged with "SystemVerilog". Pre-Verilog 2005 to me looks as crufty now as K&R (pre-ANSI C89).

> I should be able to instantiate "AXI bus" somewhere and connect things to it

There's a powerful concept called Interfaces which is pretty exactly what you just invented. You can create (and I have) an AXI Interface, even parameterized by address or data widths, etc. You can create these interfaces and connect them to modules very efficiently.

SystemVerilog/Verilog has grown to a very excessive bulky language, but unless you are doing exclusively validation/simulation and want things like UVM, the "synthesizable subset" is pretty sensible and one can very productively stick to that.

Re: Verilog Is Weird

#117

Post by fargle »

pjc50 wrote: post #31
Taniwha wrote: post #24

I think that really the hard part of learning to design chip stuff really is other stuff - understanding where/how to use storage (flops) and combinatorial logic - and simultaneity: how to handle things that happen at the same time. Initially you really need a strong understanding of digital logic (not a language), in particular pipelines. Once you have that stuff in your head you can turn to verilog (or vhdl or what…

> Once you have that stuff in your head you can turn to verilog (or vhdl or whatever) and learn how to map these ideas into the language Yes, and per the other comment this is a huge limitation of them - you don't have Javascript authors saying "you need to work out what you want in this other paradigm and then translate it". You occasionally see people writing C this way though, by working out what they want from th…

> If the main point of the language is to generate flops, flops should be an explicit primitive!

Well, firstly it isn't, as others have explained. It's broader - describe a digital logic circuit - efficiently.

Secondly, it's trivially possible to explicitly generate flip-flops and other hardware primitives using a more "structural" approach:

    DFF mydff(
      .clk (clk100),
      .rst, // means .rst(rst)
      .d   (in),
      .q   (out)
    );
Thirdly, the whole reason that we have "synthesis" is to allow a much higher-level description that is not so explicitly "structural". It gets really unwieldy otherwise:

    reg [127:0]out;
    always_ff @(posedge clk)
        out
There - I just made 128 of those flip-flops. Also, told you it was a "128 bit register that was clocked on the positive edge". One can at once describe the meaning of the circuit, describe the circuit, and make a event-driven-simulator of the circuit. For really large numbers of elements in a terse but understandable format.

It ain't perfect, but it's doing a lot more than I think a lot of people realize and a lot more than a lot of similar looking procedural languages do.

Re: Verilog Is Weird

#118

Post by phendrenad2 »

After using verilog/vhdl for awhile, I learned that trying to be "clever" in ANY way is just going to result in errors and frustration. So I write small dead-simple verilog modules, test them in isolation (icarus verilog is great! Use it with a systemverilog testbench to poke values into your module, and use gtkwave to visually verify the output), and then compose them into a larger design.

Re: Verilog Is Weird

#119

Post by exmadscientist »

mijoharas wrote: post #88

Can anyone speak about how VHDL compares to Verilog? does it suffer from the same flaws? how do they compare to one another.

They have different flaws. Neither is actually very good.

But if you are coming from the perspective of a newbie asking which to learn, there is a solid answer: absolutely, definitely, 100% learn VHDL. Do not learn Verilog. (And ignore anyone who says otherwise.)

There are two reasons for this. First, if you learn VHDL, it is then easy to learn Verilog. The reverse is not true. So even if you need to use Verilog later, and because it's more popular you probably will, this will not be difficult for you. The second reason is that VHDL makes certain very bad habits impossible at the language level (including the compiler/synthesizer). VHDL's model for how things happen is better than Verilog's, and prohibits many strange cases that you never actually want to generate. Thus, by learning VHDL, you will naturally train yourself to write code that is structurally better, and this style continues to be very successful in Verilog. In this case Verilog is too permissive: it lets you write bad code that does not map effectively to what you need. This is why it's much easier to move from VHDL to Verilog: you will not have bad habits to unlearn.

Re: Verilog Is Weird

#120

Post by jwilk »

shadowgovt wrote: post #111
jwilk wrote: post #107

Earlier quoted context omitted.

On the contrary, because parentheses are reserved, percent-encoding them is not necessarily safe: > Percent-encoding a reserved character, or decoding a percent-encoded octet that corresponds to a reserved character, will change how the URI is interpreted by most applications. https://datatracker.ietf.org/doc/html/rfc3986#section-2.2

That is, unfortunately, one of those chunks of English that is hard to interpret. "Safe" here isn't really what the RFC is talking about; the RFC is saying that if you take a URI and add or remove percent encoding for those characters, you might change the way that the URI is interpreted (because those characters mean something in the enclosing context). In other words, you can't encode or decode them without risking…

It happens that Wikipedia doesn't care whether parens are percent-encoded or not. So yes, you can use %28%29 instead (), but that's despite them being sub-delims. For example, you definitely should change & (another sub-delim) to %26 in your URLs.

And, as I noted earlier, escaping parens wouldn't even help in this case, because it's an underscore that causes the mess.

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