Earlier quoted context omitted.
RISC-V was designed to to be a teaching ISP. A minimal RISC-V is not so different from MISP. I don't think you lose much.
> RISC-V was designed to to be a teaching ISP Do you have a source for this? RISC-V always seemed like it was a production ISA from the get-go
"Provide a realistic but open ISA that captures important details of commercial generalpurpose ISA designs and that is suitable for direct hardware implementation."
"Be simple to subset for educational purposes and to reduce complexity of bringing up new implementations."
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-...
"Yunsup Lee, Krste Asanovi´c, David Patterson, and I conceived RISC-V in the summer of 2010 as an ISA for research and education at Berkeley. Two of our research ventures, RAMP Gold [92] and Maven [60], had just wound down. These projects were based around the SPARC ISA and a lightly modified MIPS ISA, respectively, and we sought to unify behind a single architecture for the next round of projects."
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-...