Arm releases experimental CHERI-enabled Morello board

> The CHERI memory-protection features allow historically memory-unsafe programming languages such as C and C++ to be adapted to provide strong, compatible, and efficient protection against many currently widely exploited vulnerabilities.

https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/

Re: Arm releases experimental CHERI-enabled Morello board

#5

Post by jrtc27 » Thu, Jan 20, 2022, 12:55 PM UTC

plutonorm wrote: post #3

I wager it will be hacked in under a year.

Nobody's claiming it's "hack-proof", that would be foolish, just that it removes certain classes of vulnerabilities that are the majority of CVEs for code written in memory-unsafe languages, thereby reducing the attack surface. Independent analysis by both Microsoft and Google has shown that's around 70% of vulnerabilities, which still leaves around 30%, but is a big step forward.

Re: Arm releases experimental CHERI-enabled Morello board

#6

Post by lacksconfidence » Thu, Jan 20, 2022, 1:12 PM UTC

jrtc27 wrote: post #5

plutonorm wrote: post #3

I wager it will be hacked in under a year.

Nobody's claiming it's "hack-proof", that would be foolish, just that it removes certain classes of vulnerabilities that are the majority of CVEs for code written in memory-unsafe languages, thereby reducing the attack surface. Independent analysis by both Microsoft and Google has shown that's around 70% of vulnerabilities, which still leaves around 30%, but is a big step forward.

Not OP, but that's not how I interpreted their comment. I interepreted it as the 70% they hope to have fixed will end up having edge cases not yet considered, and the protections will end up weaker than desired. No-one designed a processor to be susceptable to spectre and meltdown, once something moves into production there is significantly more incentive to investigate and find these flaws.

Re: Arm releases experimental CHERI-enabled Morello board

#7

Post by gchadwick » Thu, Jan 20, 2022, 1:23 PM UTC

plutonorm wrote: post #3

I wager it will be hacked in under a year.

What exactly do you mean by hacked? This isn't a product with some singular security aim, it's an evaluation platform that's come from an ongoing large research project. Previous work (using FPGA and software simulation) will have found and fixed many architectural issues. No doubt more will be found here.

In a sense the entire aim of this is for it to be 'hacked' to further improve the security architecture.

Re: Arm releases experimental CHERI-enabled Morello board

#8

Post by cosmiccatnap » Thu, Jan 20, 2022, 1:25 PM UTC

lacksconfidence wrote: post #6

jrtc27 wrote: post #5

Earlier quoted context omitted.

Nobody's claiming it's "hack-proof", that would be foolish, just that it removes certain classes of vulnerabilities that are the majority of CVEs for code written in memory-unsafe languages, thereby reducing the attack surface. Independent analysis by both Microsoft and Google has shown that's around 70% of vulnerabilities, which still leaves around 30%, but is a big step forward.

Not OP, but that's not how I interpreted their comment. I interepreted it as the 70% they hope to have fixed will end up having edge cases not yet considered, and the protections will end up weaker than desired. No-one designed a processor to be susceptable to spectre and meltdown, once something moves into production there is significantly more incentive to investigate and find these flaws.

No post body was provided.

Re: Arm releases experimental CHERI-enabled Morello board

#9

Post by pjmlp » Thu, Jan 20, 2022, 1:29 PM UTC

lacksconfidence wrote: post #6

jrtc27 wrote: post #5

Earlier quoted context omitted.

Nobody's claiming it's "hack-proof", that would be foolish, just that it removes certain classes of vulnerabilities that are the majority of CVEs for code written in memory-unsafe languages, thereby reducing the attack surface. Independent analysis by both Microsoft and Google has shown that's around 70% of vulnerabilities, which still leaves around 30%, but is a big step forward.

Not OP, but that's not how I interpreted their comment. I interepreted it as the 70% they hope to have fixed will end up having edge cases not yet considered, and the protections will end up weaker than desired. No-one designed a processor to be susceptable to spectre and meltdown, once something moves into production there is significantly more incentive to investigate and find these flaws.

There are no CVEs related to Solaris SPARC Application Data Integrity, or Unisys ClearPath MCP.

Either they aren't interesting for hackers, or they actually did a good job with hardware memory tagging.

Re: Arm releases experimental CHERI-enabled Morello board

#10

Post by thrwyoilarticle » Thu, Jan 20, 2022, 1:50 PM UTC

plutonorm wrote: post #3

I wager it will be hacked in under a year.

Do you have criticisms of the feature or is this facile cynicism?