Earlier quoted context omitted.
> RISCV architecture (a free architecture that doesn't include that shit) Surely you can't think the architecture itself is the differentiator. x86 didn't have all of this security 20 years ago, give engineers a few years of time to throw some locks on a risc-v chip and it'll be Enterprise Ready™ in no time.
With the (already?) expiration of x86 patents, I'd love to see a "pure" x86 implementation without any of the user-hostile crap, and see how far the community can take it; but sadly, the RISC bandwagon is diverting attention away from that. A CPU without the user-hostile features but still able to run the massive existing software base would be ideal.
On the other side RISCV instruction set is far simpler, being a RISC instruction set it decides to not have advanced optimizations in the processor (even better, none at all) and leave the optimization work to the compiler, that not only simplifies the processor, but also reduces the surface of attack of the processor (Meltown, Spectre, and all these attacks are just impossible on RISCV!). Of course that has a performance penalty, but since you simplify the processor you can just put more core in the saved space right?