Live data from Hacker News

Intel completely disables AVX-512 on Alder Lake after all

igorslab.de

201–210 of 317 posts

Re: Intel completely disables AVX-512 on Alder Lake after all

#201

Earlier quoted context omitted.

I've voiced this before but I think AVX-512 is completely irrelevant in the consumer space (which imho makes titles like "Intel artificially slows 12th gen down" incredulous). Even for commercial applications - sure there are some things that benefit from it. On the other hand, I work in HPC and even in (commercial, not nuke simulations or whatever the nuke powers do with their supercomputers) HPC applications AVX-51…

It is irrelevant because it is not wide-spread. AVX-512 is much nicer to program than nay previous Intel's vector instructions. It will be relevant if programmer could assume, that 50% of her auditory has CPU with AVX-512. If I want to play with it (as programmer who is interested in DSP on generic-purpose hardware) I need to rent special cloud instance for very non-hobby-friendly price. Additionally, benchamrks (of…

If you just want to play with AVX-512, you can rent an Ice Lake Xeon on AWS EC2 for only 3¢/hour, which strikes me as very hobby-friendly pricing.

Re: Intel completely disables AVX-512 on Alder Lake after all

#202
The AVX-512 rollout has been a complete disaster. Look at how quickly AVX-2 became widespread and targetable. My all metrics, AVX-512 adoption has been abysmal and most of the blame lies squarely on Intel's shoulders. And even now that platforms are beginning to support it, developers just aren't interested because AVX-2 + optimizations got them most of the way there. Then there's the heavy performance hit that regular code intermixed with AVX-512 incurs.

Re: Intel completely disables AVX-512 on Alder Lake after all

#203
post #4

Earlier quoted context omitted.

It's not even undocumented, but explicitly a documented as a feature those CPUs don't have. Originally it was supposed to be fused off physically, I wonder why it wasn't.

To get the positive wave of initial reviews from people who enable it.

Who did this? Phoronix got AVX-512 working, but was very clear that this was unexpected and had a good chance of going away before release. If anything, this is a better test for your reviewers -- if a reviewer has published benchmarks using these unsupported features without mentioning it, you should keep that in mind when listening to their reviews in the future.

Re: Intel completely disables AVX-512 on Alder Lake after all

#204

Earlier quoted context omitted.

> Librem 5 Ah yes, that phone where the FSF told them they had to move a blob from the bootloader into an external Flash memory and load it through two layers of CPUs, because going through that pointless dance magically makes it Free™ (read: hidden enough that users won't notice so they won't realize they're still running a blob as part of something as critical as making the RAM work). Also that phone which runs a p…

The point is that the proprietary software has no access to the RAM or CPU and plays absolutely no role whatsoever in the device usage. I personally agree that it can be called "hardware" and don't care that it has another CPU. The baseband is on the upgradable M.2 card, also has no access to anything. It can even be killed with a hardware switch. The best smartphone you can find if you care about it. Nobody says tha…

> The point is that the proprietary software has no access to the RAM or CPU and plays absolutely no role whatsoever in the device usage.

The proprietary software literally configures the RAM on the phone. It is critical for making the RAM work, of course it has access to the RAM! Supposedly it should be quiesced after training, but I haven't seen any security analysis that claims that firmware couldn't just take over the system while it runs.

But they added an extra two layers of indirection, even though the blob ends up running on the same CPU with the same privileges in the end anyway, because all that obfuscation let them get in via the FSF's "secondary processor" exception somehow. Even though the end result is the same, and you're still running a blob to perform a critical, security-relevant task.

If the goal is security ("blobs can't take over my system") and stuff running during the boot process doesn't count, then Apple's M1 machines are on precisely the same level as the Librem 5: they also run blobs on boot, and at runtime all remaining blobs on separate CPUs are sandboxed such that they can't take over the main RAM/CPU.

Re: Intel completely disables AVX-512 on Alder Lake after all

#205

Earlier quoted context omitted.

The point is that the proprietary software has no access to the RAM or CPU and plays absolutely no role whatsoever in the device usage. I personally agree that it can be called "hardware" and don't care that it has another CPU. The baseband is on the upgradable M.2 card, also has no access to anything. It can even be killed with a hardware switch. The best smartphone you can find if you care about it. Nobody says tha…

> The point is that the proprietary software has no access to the RAM or CPU and plays absolutely no role whatsoever in the device usage. The proprietary software literally configures the RAM on the phone . It is critical for making the RAM work, of course it has access to the RAM! Supposedly it should be quiesced after training, but I haven't seen any security analysis that claims that firmware couldn't just take ov…

You are of course right that technically it has the access to the RAM.

> Supposedly it should be quiesced after training, but I haven't seen any security analysis that claims that firmware couldn't just take over the system while it runs.

I was under impression that it was the whole point of the exercise. It would be interesting to know otherwise.

> even though the blob ends up running on the same CPU with the same privileges in the end anyway

This is not how I understood it. The Librem 5 stores these binary blobs on a separate Winbond W25Q16JVUXIM TR SPI NOR Flash chip and it is executed by U-Boot on the separate Cortex-M4F core. From here: https://source.puri.sm/Librem5/community-wiki/-/wikis/Freque....

Re: Intel completely disables AVX-512 on Alder Lake after all

#206

Earlier quoted context omitted.

> If it can be updated by the user, even if the source code is not available, it is freer than if it cannot. So we both say the same thing with different words. I agree, which is why there is a call to FSF for change. Concerning the Librem 5, if the proprietary blob can be isolated such that it can't access RAM or CPU, it's better for the user and makes the device more free, in my opinion.

> So we both say the same thing with different words. I agree, which is why there is a call to FSF for change. I thought you were saying that hardware is whatever "cannot be updated". That's the argument the FSF uses to say ROM firmware is OK because it's not software. I'm saying that's not okay, because updatability is a plus , not a minus , and ROMs are still software. > Concerning the Librem 5, if the proprietary…

> I thought you were saying that hardware is whatever "cannot be updated".

Yes, I'm saying that. But if you intentionally prevent users from updating it, then it does not turn software into hardware in my opinion.

Do you have any link saying that the blobs are still being executed on the main CPU after the RAM training is finished? Upd: you replied here: https://news.ycombinator.com/item?id=29842166.

Re: Intel completely disables AVX-512 on Alder Lake after all

#207

Stuff like this is why I plan to never buy Intel ever again. I always disliked Intel's strategy for market segmentation by disabling specific instructions, I much prefer AMD's strategy of segmenting just by speed and number of cores. It is really annoying that with Intel you can't run the same program on the server and on your desktop, it makes development and testing a huge pain.

Don't forget it's not just instruction sets; Intel is the reason we don't have ECC RAM on desktops. Every other high density storage technology has used error correction for a decade or two, but we're still sitting here pretending we can have 512 billion bits of perfect memory sitting around that will never go wrong, because Intel fuse it off on desktop chips. I guess only servers need to be reliable. AMD supports EC…

Since the Mac Pro has ECC Ram, I would expect a future Apple Silicon Mac Pro to offer it as well with its desktop M1 chip, with the functionality trickling down the line in years to come.

Re: Intel completely disables AVX-512 on Alder Lake after all

#208

Earlier quoted context omitted.

I've voiced this before but I think AVX-512 is completely irrelevant in the consumer space (which imho makes titles like "Intel artificially slows 12th gen down" incredulous). Even for commercial applications - sure there are some things that benefit from it. On the other hand, I work in HPC and even in (commercial, not nuke simulations or whatever the nuke powers do with their supercomputers) HPC applications AVX-51…

> No one claimed it was there, would work, would be stable or anything to that tune. Isn't that true of like 99.9999% of CPU features? I have never seen an Intel presentation or piece of marketing material that said my software would be able to use the EAX register, and yet it keeps showing up year after year.

Intel explicitly states which instructions sets each processor supports. They don’t list every random register or instruction. Those are captured in the detailed documents.

e.g. https://www.intel.com/content/www/us/en/products/sku/226066/...

Re: Intel completely disables AVX-512 on Alder Lake after all

#209

Earlier quoted context omitted.

> The point is that the proprietary software has no access to the RAM or CPU and plays absolutely no role whatsoever in the device usage. The proprietary software literally configures the RAM on the phone . It is critical for making the RAM work, of course it has access to the RAM! Supposedly it should be quiesced after training, but I haven't seen any security analysis that claims that firmware couldn't just take ov…

You are of course right that technically it has the access to the RAM. > Supposedly it should be quiesced after training, but I haven't seen any security analysis that claims that firmware couldn't just take over the system while it runs. I was under impression that it was the whole point of the exercise. It would be interesting to know otherwise. > even though the blob ends up running on the same CPU with the same p…

> I was under impression that it was the whole point of the exercise. It would be interesting to know otherwise.

It absolutely wasn't. Look into it. In every case, the blob ends up running on the RAM controller CPU and supposedly finishes running and is done. The whole point of the exercise was obfuscating the process which is used to get to that point such that it avoided the main CPU physically moving the bits of the blob from point A to point B. Really.

> This is not how I understood it. The Librem 5 stores these binary blobs on a separate Winbond W25Q16JVUXIM TR SPI NOR Flash chip and it is executed by U-Boot on the separate Cortex-M4F core.

That is incorrect (great, now they either don't know how their own phone works or they're lying - see what I said about obfuscation? It's great for confusing everyone).

The M4 core code is not proprietary; it's the pointless indirection layer they wrote and it is not loaded from that SPI NOR flash. It's right here:

https://source.puri.sm/Librem5/Cortex_M4/-/tree/master

That open source code, which is loaded by the main CPU into the M4 core, is responsible for loading the RAM training blob from SPI flash (see spi.c) and into the DDR controller (see ddr_loader.c).

The actual blob then runs on the PMU ("PHY Micro-Controller Unit") inside the DDR controller. This is an ARC core that is part of the Synopsys DesignWare DDR PHY IP core that NXP licensed for their SoC. Here, cpu_rec.py will tell you:

  firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem.bin
      full(0x5ac0)   ARcompact                          chunk(0x4e00;39)    ARcompact 
The normal way this is done is the DDR training blob is just embedded into the bootloader like any other data, and the bootloader loads it into the PMU. Same exact end result, minus involving a Cortex-M4 core for no reason and minus sticking the blob in external flash for no reason. Here, this is how U-Boot does it on every other platform:

https://github.com/u-boot/u-boot/blob/master/drivers/ddr/imx...

Same code, just running on the main CPU because it is absolutely pointless running it on another core, unless you're trying to obfuscate things to appease the FSF. And then the blob gets appended to the U-Boot image post-build (remember this just gets loaded into the PMU, it never touches the main CPU's execution pipeline):

https://github.com/u-boot/u-boot/blob/master/tools/imx8m_ima...

Purism went out of their way and wasted a ton of engineering hours just to create a more convoluted process with precisely the same end result, because somehow all these extra layers of obfuscation made the blob not a blob any more in the FSF's eyes.

The security question here is whether that blob, during execution, is in a position to take over the system, either immediately or somehow causing itself to remain executing. Can it only talk to the RAM or can it issue arbitrary bus transactions to other peripherals? Can it control its own run bit or can the main CPU always quiesce it? Can it claim to be "done" while continuing to run? Can it misconfigure the RAM to somehow cause corruption that allows it to take over the system? I have seen no security analysis to this effect from anyone involved, because as far as I can tell nobody involved cares about security; the whole purpose of this exercise obviously wasn't security, it was backdooring the system into RYF compliance.

Re: Intel completely disables AVX-512 on Alder Lake after all

#210

Earlier quoted context omitted.

As my link already says, the FSF can and should be improved. However, I think there is a point in separating "hardware" from "software", where the former is not to be updated. If it can be updated by anyone, in any way, it's not hardware.

If it can be updated by the user, even if the source code is not available, it is freer than if it cannot. Because then users can actually see the code, reverse engineer it, audit it, know they are running the exact version they expect, and potentially replace it with a free one. This concept that "if it's in ROM and cannot be updated it's not software, it's hardware" is asinine, against actual practical freedom for…

> This concept that "if it's in ROM and cannot be updated it's not software, it's hardware" is asinine, against actual practical freedom for users, and also a net security negative.

There is a distinction between blob 'is in ROM and cannot be updated', 'is in EPROM and might be updated', and 'it is in RAM and must be provided at boot'.

While one can argue about the second case, the third case is problematic for practical and legal reasons, as handling (using and distributing) requires accepting licence of the firmware, which affects distribution infrastructure of free Linux distributions. Some firmwares also do not allow redistributing, so they have to be downloaded from vendor website, which further complicates practical and legal matters and have privacy issues.

The second case (it is in EPROM nad might be updated) does not have such effect directly, but leads to it indirectly, by allowing vendors to depend on cheap post-purchase fixes by firmware update, so they can offer less tested products, where firmware update is practically necessary due to original firmware being buggy, so essentially moving to the third case.

Post reply on HN