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Intel completely disables AVX-512 on Alder Lake after all

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Re: Intel completely disables AVX-512 on Alder Lake after all

#101

Post by xlazom00 »

square_usual wrote: post #44
codeflo wrote: post #11

If all of this was planned (and I’m not saying it is), that would have been very clever. It would work like this: 1. You “accidentally forget” to disable the feature in hardware. Given how competitive the market is, motherboard manufacturers can be relied upon to enable it in their “1337 OVERCLOCKZ” mode. No conspiracy is needed. 2. You “tolerate” this practice just long enough to win the critical initial wave of rev…

Is AVX-512 even useful in benchmarks? I thought it was mostly used for specialized workloads, and was basically useless for end users and gamers.

Specialized like software video decoding and encoding,....

Re: Intel completely disables AVX-512 on Alder Lake after all

#102

Post by gambiting »

adrian_b wrote: post #35
gambiting wrote: post #7

Earlier quoted context omitted.

It was never advertised, and Intel very specifically said AVX-512 instructions will not be available. Some motherboard manufacturers made them available anyway, now Intel is fixing that. It's like buying a car with an advertised speed limiter of 155mph, then finding that actually it can go 170mph, and then the manufacturer fixes the speed limiter with a software update. Yes we know the car could go faster, but the sp…

Intel very specifically said that AVX-512 instructions will not be available only a few weeks before the Alder Lake launch. While it cannot be said that Intel advertised AVX-512 for Alder Lake, at all previous disclosures it was said that the Golden Cove cores have AVX-512 and the Gracemont cores do not have it. It was clearly said that in hybrid configurations AVX-512 will be disabled, because for Microsoft it is a…

>>Whether AVX-512 can be enabled by disabling the Gracemont cores was not said

Reading up on it, I was under the impression that's exactly how it worked, no? If you disable the efficiency cores in BIOS, the enable AVX-512 option would appear on selected few motherboards. You can't have all cores enabled and keep AVX-512 enabled at the same time.

Re: Intel completely disables AVX-512 on Alder Lake after all

#103

Post by my123 »

marcan_42 wrote: post #87
Karunamon wrote: post #77

Earlier quoted context omitted.

ECC memory on the other hand is always going to be more expensive.

Indeed, which is why it should be an option. OTOH, it shouldn't be significantly more expensive. It should be ~9/8 the cost of regular memory. It's just one extra chip for every 8. Nothing more.

in-band ECC is also a thing. In that scenario, you give up some capacity for the ECC bits but stay with the same DRAM config as before.

(in-band ECC is present on Elkhart Lake Atoms and on Tegra Xavier for example)

Re: Intel completely disables AVX-512 on Alder Lake after all

#104

Post by davidlt »

jsnell wrote: post #4
MauranKilom wrote: post #3

Earlier quoted context omitted.

This is an undocumented feature, from what I gather. So it's missing the "bait" part of "bait and switch".

It's not even undocumented, but explicitly a documented as a feature those CPUs don't have. Originally it was supposed to be fused off physically, I wonder why it wasn't.

It could be that decision to not support AVX512 was made very late in product development and thus early batches didn't have chicken bit disabled or/and fused it off.

There might be gazillions of reason why this was done.

Re: Intel completely disables AVX-512 on Alder Lake after all

#105

Post by GeekyBear »

Once power and heat in a chip go high enough, Electromigration causes reliability issues.

It was already thought that this would become a problem to worry about at smaller process nodes, but does AVX-512 on Alder Lake push voltage and heat enough that it is an issue already?

>Electromigration is the movement of atoms based on the flow of current through a material. If the current density is high enough, the heat dissipated within the material will repeatedly break atoms from the structure and move them. This will create both ‘vacancies’ and ‘deposits’. The vacancies can grow and eventually break circuit connections resulting in open-circuits, while the deposits can grow and eventually close circuit connections resulting in short-circuit.

https://www.synopsys.com/glossary/what-is-electromigration.h...

>Aging Problems At 5nm And Below

https://semiengineering.com/aging-problems-at-5nm-and-below/

Re: Intel completely disables AVX-512 on Alder Lake after all

#106

Post by FrostKiwi »

PragmaticPulp wrote: post #91
formerly_proven wrote: post #73

Earlier quoted context omitted.

I've voiced this before but I think AVX-512 is completely irrelevant in the consumer space (which imho makes titles like "Intel artificially slows 12th gen down" incredulous). Even for commercial applications - sure there are some things that benefit from it. On the other hand, I work in HPC and even in (commercial, not nuke simulations or whatever the nuke powers do with their supercomputers) HPC applications AVX-51…

> I've voiced this before but I think AVX-512 is completely irrelevant in the consumer spac Don’t forget that reviewers made a huge deal out of the fact that CPUs downclock themselves when running AVX instructions. Several reviewers tried to make this into some sort of scandal at the time, which I’d guess contributed to Intel wanting to remove the feature from consumer CPUs. Of course, many of those same reviewers ar…

> Don’t forget that reviewers made a huge deal out of the fact that CPUs downclock themselves when running AVX instructions.

It was and is kinda a huge deal. I followed the development of Corona Renderer for the past decade closely and one reoccuring theme with conflicting evidence was whether the inclusion of AVX was beneficial or detremental to performance due to resulting down clocking on certain platforms.

And surprisingly, now quickly looking through the search function, of the corona renderer forum an update apparently even dropped AVX because of better performance. ( https://forum.corona-renderer.com/index.php?topic=33889.msg1... ) Though I wonder if this is accurate or if the post is missing context...

Re: Intel completely disables AVX-512 on Alder Lake after all

#107

Post by marcan_42 »

nullify88 wrote: post #59
marcan_42 wrote: post #26

Earlier quoted context omitted.

I'm pretty sure downgrades are blocked. You need to hack the BIOS so the (volatile) upgrade never happens on boot.

I wouldnt call it hacking. If you can find or backup the bios image for your motherboard, you can replace the microcode in it and reflash. Bios images are modular and the microcode is a replacable component.

Hacking BIOS images isn't always that easy. Often they are signed (EFI Capsules) and the standard update utility in the BIOS menu will reject modified versions. I had to use a convoluted flashing process to make a trivial patch to a BIOS a few years back for this reason.

Re: Intel completely disables AVX-512 on Alder Lake after all

#108

Post by marcan_42 »

3836293648 wrote: post #64
marcan_42 wrote: post #26

Earlier quoted context omitted.

I'm pretty sure downgrades are blocked. You need to hack the BIOS so the (volatile) upgrade never happens on boot.

Microcode updates are applied at runtime, every time you boot them. At least on the CPU side. The motherboard might apply them before the OS loads though, so who knows what happens there

Thats what I said; the updates are volatile but the OS can't undo an update that the BIOS already applied on boot.

Re: Intel completely disables AVX-512 on Alder Lake after all

#109

Post by philliphaydon »

neogodless wrote: post #80
philliphaydon wrote: post #53

Earlier quoted context omitted.

The ryzen 6000 series for laptops will support usb 4 with tb3. What does tb4 offer over 3?

https://plugable.com/blogs/news/what-s-the-difference-betwee... The short answer for Thunderbolt 4 over Thunderbolt 3 is "a second 4K display" thanks to double the PCIe bandwidth, 16Gbps vs 32Gbps. (The main data channel is 40Gbps in both.) USB 4 is actually a bit more constrained than Thunderbolt 3, at 20Gbps data channel, and no guarantee of PCIe bandwidth. > Thunderbolt 4 guarantees support for one 8K display or t…

So it sounds like TB3 + USB4 would be a good docking station, and TB4 just makes it a bit better. So I shouldn't be too worried if I upgrade my laptop and it only has TB3.

Finding it hard to keep up with tech lately :D

Re: Intel completely disables AVX-512 on Alder Lake after all

#110

Post by adrian_b »

gambiting wrote: post #102
adrian_b wrote: post #35

Earlier quoted context omitted.

Intel very specifically said that AVX-512 instructions will not be available only a few weeks before the Alder Lake launch. While it cannot be said that Intel advertised AVX-512 for Alder Lake, at all previous disclosures it was said that the Golden Cove cores have AVX-512 and the Gracemont cores do not have it. It was clearly said that in hybrid configurations AVX-512 will be disabled, because for Microsoft it is a…

>>Whether AVX-512 can be enabled by disabling the Gracemont cores was not said Reading up on it, I was under the impression that's exactly how it worked, no? If you disable the efficiency cores in BIOS, the enable AVX-512 option would appear on selected few motherboards. You can't have all cores enabled and keep AVX-512 enabled at the same time.

This was possible on most motherboards at launch.

Now however, Intel has issued a BIOS update that no longer allows enabling AVX-512 when the Gracemont cores are disabled.

The motherboards produced from now on will have the new BIOS version.

Keeping the original BIOS on the existing Alder Lake motherboards is not a good choice, because the new BIOS version also improves stability in certain memory configurations.

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