Warning, PDF link.
Content-Disposition: attachment warning too. I hate when sites force me to save files when I can easily view them right in my browser.
Maxwell, A 64 FPGA Supercomputer (pdf)
11–20 of 25 posts
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#12Not to rain on anyone's parade, but next to my desk is a machine about 10 times more powerful than what this paper describes. The main issues with the setup in the paper: latency between nodes. Gigabit Ethernet is just not good for latency. To nitpick some more, Virtex-4 is getting old.
I definitely agree about GE being a bad choice, I suspect that something like HT would work better for this application. I wouldn't be concerned about Virtex-4 being old, being used as a proof of concept for this should at least give some indication of how the design of the whole thing scales and give some idea of the problems that will come about, latency being one of them.
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#13Not to rain on anyone's parade, but next to my desk is a machine about 10 times more powerful than what this paper describes. The main issues with the setup in the paper: latency between nodes. Gigabit Ethernet is just not good for latency. To nitpick some more, Virtex-4 is getting old.
The pig dances, I'm sure that over time it will learn how to dance better.
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#14Yet another FPGA vs CPU paper that doesn't compare with GPU's as well.
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#15Yet another FPGA vs CPU paper that doesn't compare with GPU's as well.
And why should it? The CPU and the GPU are entirely different beasts.
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#16Earlier quoted context omitted.
Title updated, thanks!
Great paper -- thank you! When is the publish date? 2008/2009?
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#17Wall clock time alone isn't such a useful metric to compare CPU vs. FPGA. It would be more meaningful to normalize by machine cost (initial investment and operating costs). (Software development/non-portability is a separate discussion.)
They address software development cost at the end of the paper, and basically conclude that FPGAs are too hard to program to replace CPUs yet, even for highly specialized HPC applications.
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#18Yet another FPGA vs CPU paper that doesn't compare with GPU's as well.
And why should it? The CPU and the GPU are entirely different beasts.
That was true 5 years ago, but not today; GPUs and CPUs are converging. GPUs are quite suitable for all of the applications described in the article, and provide orders of magnitude speedup over CPUs while remaining relatively cheap and easy to program vs. FPGAs.
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#19Wall clock time alone isn't such a useful metric to compare CPU vs. FPGA. It would be more meaningful to normalize by machine cost (initial investment and operating costs). (Software development/non-portability is a separate discussion.)
They address software development cost at the end of the paper, and basically conclude that FPGAs are too hard to program to replace CPUs yet, even for highly specialized HPC applications.
My point is that they should demonstrate what the potential hardware advantage is before evaluating whether the software development costs are worthwhile. There are a few HPC tasks that are very simple and possibly amenable to specialized hardware. D.E. Shaw's Anton is an extreme example of pursuing dedicated hardware. But the metric needs to involve purchasing and power costs for the hardware. FPGAs can come out looking very good in this metric, but comparing raw run times for different systems without cost normalization is meaningless.
Re: Maxwell, A 64 FPGA Supercomputer (pdf)
#20Not to rain on anyone's parade, but next to my desk is a machine about 10 times more powerful than what this paper describes. The main issues with the setup in the paper: latency between nodes. Gigabit Ethernet is just not good for latency. To nitpick some more, Virtex-4 is getting old.
Gigabit Ethernet is mainly used as a control network. Each FPGA has 4 RocketIO links (2-3Gb/s) and they are directly connected in a 2-D torus of point-to-point links. The RocketIO network is used for nearest-neighbor communication patterns. For reduction operations such as global sums, they call back to the host CPUs for MPI reduction operations to be preformed over the GE network.
Also one of the main goals was to build the supercomputer from commodity parts and "plug-in" FPGA cards, so they most likely had to go with FPGA cards there where available and maybe cheaper then the latest/greatest.
The paper would have been more interesting if they had compared this machine to other types of supercomputers then just CPU clusters.