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SPI: The serial peripheral interface [video]

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Re: SPI: The serial peripheral interface [video]

#31

Post by jstanley »

monocasa wrote: post #23
jstanley wrote: post #21

Earlier quoted context omitted.

No, I don't, but at the point where you're integrating a UART, adding a couple of logic gates on the data input doesn't seem too much of a stretch. I'm not saying using UARTs instead of SPI is a good idea! I'm just saying the reason that it's not a good idea is not because UART's don't have /SS inputs.

But then how is the device supposed to know when it can respond? Most uart devices don't respect flow control. They assume they can transmit at any point.

Fair point.

Re: SPI: The serial peripheral interface [video]

#32

Post by Taniwha »

SV_BubbleTime wrote: post #28
Taniwha wrote: post #20

Earlier quoted context omitted.

In my experience has been that there exist essentially 2 types of SPI, one addressable by CS, the other (more i2c-like) by the first byte (CS still required to frame the transactions. I'm working with one of the latter type at the moment that's even worse, it daisy chains chips with each editing the address as it passes through until it hits one where it's 0, they share a CS and a wired-or interrupt, but avoid the ne…

I’ve never seen SPI that doesn’t require a CS line. The whole way that daisy chaining works is this. Do you have a device off hand that uses addressable SPI, I want to see how they explain it in a datasheet.

I'm afraid the two I can think of have non-publicly available data sheets: one is a cablecrypto device, the other a SLIC. The SLIC is the one with the daisy chain - they want to be able to build phone systems with a SLIC for every slot in a T1 frame - so 24 SLICs - they're trying to avoid 24 CS pins and 24 interrupts on the attached signalling CPU
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