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Computing Performance on the Horizon

brendangregg.com

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Re: Computing Performance on the Horizon

#41

Post by dragontamer »

infogulch wrote: post #38
ksec wrote: post #27

>for storage including new uses for 3D Xpoint as a 3D NAND accelerator; 3D XPoint's future is not entirely certain. Intel with their new CEO has remained rather quiet on the subject. Micron are pulling the plug on it and sold the Fab to Texas Instrument. The problem is there isn't a clear path forward with the technology, it make some sense when NAND and DRAM price were high in 2016 - 2019. Once they dropped to a nor…

> Are there really no use-case where 128 Core+ with NUMA offer some advantage? Are there any use cases where 128+ core single socket wouldn't be preferred to a 128+ core multiple socket design that is burdened by NUMA? AMD has been showing us that integrating the interconnects into the CPU package directly and letting it handle all the issues is a better design.

When a hypothetical 128-core single socket comes out, will there be no workload that prefers to use a 2x128-core dual socket instead?

AMD CPUs remain largely dual-socket compatible. Today's 64-core EPYCs can be dual-socketed into 2x64-core beasts.

It just seems silly to me that if you're building say 200 computers in 10x racks (20-computers per 10x 40U racks) that you'd prefer single socket over dual-socket. If you're scaling up and out so much, what exactly is the problem with dual socket? Its not costs: dual socket remains cost-effective on a per-core basis over single-socket. Dual-sockets cuts the number of computers you need to work with in half. Etc. etc.

Re: Computing Performance on the Horizon

#42

Post by nradov »

thechao wrote: post #40
nradov wrote: post #32

Earlier quoted context omitted.

How are we going to cool those 3D chips?

The commenter above is correct: just stop toggling HW. We already do this to a great extent; we’re limited in the number of custom implementations because we can’t wire everything together. 3D chips will have a lot more “dark” logic than current chips, but will be orders-of-magnitude more efficient (& thus powerful) due to deep customization. Also, remember the argument of my timeline is ~50–80 years out from now.

Dark logic isn't doing any useful work so what's the point? Sure you can include specialized circuitry for a bunch of rare cases, but that won't lift overall system performance much and will kill manufacturing yields.

Re: Computing Performance on the Horizon

#43

Post by rbanffy »

I have an enormous respect for Brandon Gregg, but this "one socket ought to be enough for anyone" is something I saw too many people get burned with.

I mean, it should, but who knows what the next version of Slack will need...

Re: Computing Performance on the Horizon

#44

Post by justicezyx »

martinpw wrote: post #10

Slide 26 is interesting - arguing that cloud providers have an advantage for future CPU design since they can analyze so many real world customer workloads directly. In previous roles I have worked with CPU vendors who have been very keen on getting access to profiling data from our workloads for design optimization, and lamenting the fact that it was hard to get such data and they were often limited to synthetic ben…

It's already happening. Intel design now are significantly influenced by Google and Amazon's data center needs.

Re: Computing Performance on the Horizon

#45

Post by thechao »

nradov wrote: post #42
thechao wrote: post #40

Earlier quoted context omitted.

The commenter above is correct: just stop toggling HW. We already do this to a great extent; we’re limited in the number of custom implementations because we can’t wire everything together. 3D chips will have a lot more “dark” logic than current chips, but will be orders-of-magnitude more efficient (& thus powerful) due to deep customization. Also, remember the argument of my timeline is ~50–80 years out from now.

Dark logic isn't doing any useful work so what's the point? Sure you can include specialized circuitry for a bunch of rare cases, but that won't lift overall system performance much and will kill manufacturing yields.

The GPU in your computer consists of mostly-dark highly specialized circuits; it certainly seems to improve my computing experience.

Re: Computing Performance on the Horizon

#46

Post by brendangregg »

martinpw wrote: post #10

Slide 26 is interesting - arguing that cloud providers have an advantage for future CPU design since they can analyze so many real world customer workloads directly. In previous roles I have worked with CPU vendors who have been very keen on getting access to profiling data from our workloads for design optimization, and lamenting the fact that it was hard to get such data and they were often limited to synthetic ben…

Thanks, I think it's the start of a new "cloud CPU" era.

Cloud vendors have already split workloads into different instance types, so directly analyzing their workloads and developing CPUs for each instance type will lead to further performance wins. This may prompt the creation of even more instance types just to further separate workload types for future CPU specialization.

In the future, products like AWS outposts may become far more desirable over commodity hardware, as customers know it provides access to specialized CPUs and their performance. It's a path for cloud computing vendors to own the datacenters as well.

(Note that my predictions are not based on any internal knowledge: I'm just describing what I personally would be doing if I were a cloud vendor.)

Re: Computing Performance on the Horizon

#47

Post by brendangregg »

justicezyx wrote: post #44
martinpw wrote: post #10

Slide 26 is interesting - arguing that cloud providers have an advantage for future CPU design since they can analyze so many real world customer workloads directly. In previous roles I have worked with CPU vendors who have been very keen on getting access to profiling data from our workloads for design optimization, and lamenting the fact that it was hard to get such data and they were often limited to synthetic ben…

It's already happening. Intel design now are significantly influenced by Google and Amazon's data center needs.

Sure, and I have regular meetings with processor vendors who want to understand our workload to better serve it. But there's no easy or fast way for them to get low-level data, including processor trace (cycle logs), across many customers. This can be vast amounts of data: Tbytes. If you are working on processors at a cloud vendor and want to know some low-level CPU detail, you could answer it immediately across a million customer workloads.

Re: Computing Performance on the Horizon

#48

Post by wmf »

zozbot234 wrote: post #28
zaroth wrote: post #15

Earlier quoted context omitted.

In my very limited experience it seems like space is much less an issue than power density. You can fit far more kW/U than the datacenter can possibly cool. In the commodity space that I rent, I ran out of power before filling even half the rack. I’m sure higher power/cooling density is possible to obtain, but I would think you’re primarily paying for that versus square footage?

What do you need that power density for? It's a rack, not a supercomputer. (I sure hope it's not "mining coins" or anything like that.)

It's not really about needing power density; high density can easily happen accidentally. 40 1S servers in a rack could be 20 kW and 40 2S servers could be 30+ kW.

Re: Computing Performance on the Horizon

#49

Post by hinkley »

rbanffy wrote: post #43

I have an enormous respect for Brandon Gregg, but this "one socket ought to be enough for anyone" is something I saw too many people get burned with. I mean, it should, but who knows what the next version of Slack will need...

Still feels to me like we should be going the other way - kick more and more things off of the motherboard and support them with discrete - potentially customized - processors of their own.

Between io_uring and current or future facilities of eBPF, we have a lot of tools on deck for pipelining IO operations, and once you have a way to pipeline IO operations, the latency is not the only bottleneck. Then it’s a matter of how much bandwidth you can push between two processes, or processors.

Re: Computing Performance on the Horizon

#50

Post by blt »

yjftsjthsd-h wrote: post #33
thechao wrote: post #26

Earlier quoted context omitted.

He sort of implies that “just better hardware” will peter out in the 2030s. I think he’s calling it at least 50 years too soon. Here’s why: (1) I think logic designers are still faffing about in term of optimizing their designs; and (2), I think there’s a lot of smart people thinking “incrementally” through what we’d consider paradigm shifts in HW implementation. That is, our fabs will just naturally segue into 3D, s…

> in 2D layout is NP-hard (complete) without efficient polynomial approximations; in 3D layout is low-order polynomial Any chance you could explain to a novice why 3D is easier? To my naive intuition, it would have seemed like the more room to maneuver is offset by having more stuff to route.

Intuitively, we feel that larger solution spaces should make a problem harder because there are more possible solutions to consider. And of course this is true if exhaustive search is the only algorithm.

But CS is full of problems where the smaller space is NP-hard and the larger one isn't. Integer linear programming is a prominent example.

To resolve the intuition, we can think of the larger space as an "unconstrained" problem where the solution space is somehow natural and nice for the problem. From this perspective, the smaller space looks like an added constraint. Adding constraints usually makes problems harder.

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