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Cerebras’ new monster AI chip adds 1.4T transistors

spectrum.ieee.org

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Re: Cerebras’ new monster AI chip adds 1.4T transistors

#11

Post by systemvoltage »

bob1029 wrote: post #9
systemvoltage wrote: post #3

Most interesting aspect of wafer-scale manufacturing is yield. Even if we have 95% chip yield, as the chip size approaches the wafer-level dimensions, I don't know off top of my head what the math would be but it is going to plummet drastically. My guess is that they're handling this in the chip logic. Building resiliency by turning off cells in the wafer that didn't yield. That begs the question, how are they probin…

They probably aren't bothering to. The extreme economics for producing this type of chip are likely acceptable to the stakeholders. Also, there is no reason they cant have some redundancy throughout the design so you can fuse off bad parts. It all really depends on the nature of the anticipated vs actual defects, which is an extraordinarily deep rabbit hole to climb into.

I wonder how much this "chip" costs!

Re: Cerebras’ new monster AI chip adds 1.4T transistors

#12

Post by seniorivn »

systemvoltage wrote: post #3

Most interesting aspect of wafer-scale manufacturing is yield. Even if we have 95% chip yield, as the chip size approaches the wafer-level dimensions, I don't know off top of my head what the math would be but it is going to plummet drastically. My guess is that they're handling this in the chip logic. Building resiliency by turning off cells in the wafer that didn't yield. That begs the question, how are they probin…

they exclude/disable cores with issues so an long as infrastructure parts of the chip are not affected the chip is functional

Re: Cerebras’ new monster AI chip adds 1.4T transistors

#14

Post by LASR »

systemvoltage wrote: post #11
bob1029 wrote: post #9

Earlier quoted context omitted.

They probably aren't bothering to. The extreme economics for producing this type of chip are likely acceptable to the stakeholders. Also, there is no reason they cant have some redundancy throughout the design so you can fuse off bad parts. It all really depends on the nature of the anticipated vs actual defects, which is an extraordinarily deep rabbit hole to climb into.

I wonder how much this "chip" costs!

Products like these are often sold as part of a contract to deliver complete solutions + support + maintenance over some number of years.

It's hard to estimate a per-unit cost. But suffice to say it would cost similar to other datacenter compute solutions on a performance/$ level.

Re: Cerebras’ new monster AI chip adds 1.4T transistors

#18

Post by Pet_Ant »

bob1029 wrote: post #9
systemvoltage wrote: post #3

Most interesting aspect of wafer-scale manufacturing is yield. Even if we have 95% chip yield, as the chip size approaches the wafer-level dimensions, I don't know off top of my head what the math would be but it is going to plummet drastically. My guess is that they're handling this in the chip logic. Building resiliency by turning off cells in the wafer that didn't yield. That begs the question, how are they probin…

They probably aren't bothering to. The extreme economics for producing this type of chip are likely acceptable to the stakeholders. Also, there is no reason they cant have some redundancy throughout the design so you can fuse off bad parts. It all really depends on the nature of the anticipated vs actual defects, which is an extraordinarily deep rabbit hole to climb into.

How does this fusing work? I assume there are a bunch of wires than are either hot or ground and that determines if part of a chip gets run?

Re: Cerebras’ new monster AI chip adds 1.4T transistors

#19

Post by etaioinshrdlu »

How much memory is on the chip, and what kind is it?

Under what circumstances does the chip need to access external memory?

What type of communication interfaces does this chip have?

Also, if the chip is the size of a wafer, is it appropriate to call it a Chip?

Re: Cerebras’ new monster AI chip adds 1.4T transistors

#20

Post by punnerud »

tandr wrote: post #15

How do they do heat management and dissipation on such a big wafer? I can imagine some different parts heats up differently, putting a mechanical strain on wafer, and leading to cracks.

A large portion of the article is answering most of this
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