How did SiFive get anywhere near 5nm TSMC?
"The tape out means that the documentation for the chip has been submitted for manufacturing to TSMC, which essentially means that the SoC has been successfully simulated. The silicon is expected to be obtained in Q2 2021." Would this mean the actual chip delivery may still be delayed?
For a small volume ‘shuttle’ run hopefully there won’t be delays, but this is not the same as having working chips!
The foundry will do initial checks it is manufacturable at ‘tapeout’ when you submit your design, but you don’t know for sure if your chip works with intended functionality until you get it back! You are relying on lots and lots of simulations up front before your ‘tape-out’.
Sometimes issues are found and a chip requires a re-spin - basically another go with the bugs fixed. You want to do this as few times as possible (ideally right first time) due to cost and time of these iterations.