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AMD 3rd Gen EPYC Milan Review

anandtech.com

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Re: AMD 3rd Gen EPYC Milan Review

#61

Post by justincormack »

dragontamer wrote: post #44
cm2187 wrote: post #37

Earlier quoted context omitted.

I am building a single socket server right now, I can't really justify more than twice the price of a 7443P for a marginally higher base clock and twice the cache. Does the cache makes that much of a difference? I thought these are already very large caches vs lots of Intel CPUs.

Hmm, with AMD Threadripper, you're already looking at TLB issues at these L3 sizes. So if you actually want to take advantage of lots of L3, you need either many cores, or hugepages. Case in point: AMD Zen2 has 2048 TLB entries (L2), under a default (in Linux and Windows) of 4kB per TLB entry. That's 8MBs of TLB before your processor starts to page-walk. Emphasis: Your application will pagewalk when the data still fi…

The 64k page size available on Arm (and Power) makes a lot more sense with these kind of cache sizes. With 2MB amd64 hugepages its only 16 different pages in that L3 cache, which for a cluster of up to 8 CPUs is not much at all when using huge pages.

Re: AMD 3rd Gen EPYC Milan Review

#62

Post by wtallis »

willis936 wrote: post #4
modzu wrote: post #2

how is a 300W cpu cooled in a server environment? just high rpms and good environmentals? ive stayed on intel with my workstation so i can keep a virtually passive and quiet heatsink without having to go water

Servers are in 4U rack mounted enclosures with (relatively) low height heatsinks and huge amounts of airflow. Intake in front, exhaust in rear. Most clients will have beefy air conditioning to keep the ambient intake temp and humidity low.

I think 4U servers are quite rare these days, except for models designed to accommodate large numbers of either GPUs or 3.5" hard drives. Most 2-socket servers with up to a few dozen SSDs are 2U designs.

Re: AMD 3rd Gen EPYC Milan Review

#63

Post by dragontamer »

justincormack wrote: post #61
dragontamer wrote: post #44

Earlier quoted context omitted.

Hmm, with AMD Threadripper, you're already looking at TLB issues at these L3 sizes. So if you actually want to take advantage of lots of L3, you need either many cores, or hugepages. Case in point: AMD Zen2 has 2048 TLB entries (L2), under a default (in Linux and Windows) of 4kB per TLB entry. That's 8MBs of TLB before your processor starts to page-walk. Emphasis: Your application will pagewalk when the data still fi…

The 64k page size available on Arm (and Power) makes a lot more sense with these kind of cache sizes. With 2MB amd64 hugepages its only 16 different pages in that L3 cache, which for a cluster of up to 8 CPUs is not much at all when using huge pages.

TLB-misses always slows down your code, even out-of-cache.

So having 2MB (or even 1GB) hugepages is a big advantage in memory-heavy applications, like databases. No, 1GB pages won't fit in L3 cache, but it still means you won't have to page-walk when looking for memory.

1GB pages might be too big for today's computers, but 2MB pages might be good enough for default now. Historically, 4kB was needed for swap purposes (going to 2MB with Swap would incur too much latency if data paged out), but with 32GBs RAM + SSDs on today's computers... fewer and fewer people seem to need swap.

There might be some kind of fragmentation-benefit for using the smaller pages, but it really is a hassle for your CPU's TLB to try to keep track of all that virtual memory and put it back in order.

---------

While there is performance hits associated with page-walks, the page-walk process is fortunately pretty fast. So most applications probably won't notice a major speedup... still though, the idea of tons of unnecessary page-walks slowing down untold amounts of code bothers me a bit for some reason.

Note: ARM also supports hugepages. So going up to 2MBs (or bigger) on ARM is also possible.

Re: AMD 3rd Gen EPYC Milan Review

#64

Post by blagie »

IanCutress wrote: post #50
dragontamer wrote: post #43

Earlier quoted context omitted.

Considering both are made from the 7nm TSMC process, AMD probably aren't going to make any more Zen2 processors at this point. I think you're right: that buying a generation old or so can offer gross cost savings. But that's only true for the time-period where those chips are available.

AMD is going to keep Zen 2 EPYC sales going for a good while yet. Both families will co-exist in the market.

I suspect so. A lot of the commercial market wants stability. Once I've validated a server config for a particular use, I want to be able to continue building those servers for a long time (often long past obsolescence).

That may seem odd, but a lot of safety-critical applications (e.g. medical, military, aerospace, etc.) require spending tens of thousands, hundreds of thousands of dollars, or even millions of dollars (not to mention months of time) re-validating a system with any substantive change.

Even for less critical applications, spending $2000 extra on each CPU is a bargain compared to re-validating a system.

If AMD wants to be a credible presence in those markets, and I'm pretty sure it does, it needs to chips with many year lifespans before EOL.

Some companies manage this by having a subset of devices or of software which is LTS.

Re: AMD 3rd Gen EPYC Milan Review

#65

Post by rodgerd »

modzu wrote: post #2

how is a 300W cpu cooled in a server environment? just high rpms and good environmentals? ive stayed on intel with my workstation so i can keep a virtually passive and quiet heatsink without having to go water

Servers are horrifyingly loud, and datacentres will destroy your hearing in no time flat. Airflow management in datacentres is quite the art form, as well: proper packing of the racks for airflow, height of raised floors to accommodate blown air, and so on; some people are starting to go back to the future with things like liquid-cooled racks as well.

Re: AMD 3rd Gen EPYC Milan Review

#66

Post by gameswithgo »

ChuckMcM wrote: post #58

Nice bump in specs. Perhaps now they will announce the Zen3 Threadripper :-). As others have mentioned the TR can starve itself on memory accesses when doing a lot of cache invalidation (think pointer chasing through large datasets). If the EPYC improvement of having the chiplet CPUs all share L3 cache moved into the TR space (which one might assume it would[1]) then this could be a reason to upgrade. [1] I may be wr…

yes TR will have the new cache configuration, just like regular ryzen and epyc do.

Re: AMD 3rd Gen EPYC Milan Review

#67

Post by touisteur »

wtallis wrote: post #62
willis936 wrote: post #4

Earlier quoted context omitted.

Servers are in 4U rack mounted enclosures with (relatively) low height heatsinks and huge amounts of airflow. Intake in front, exhaust in rear. Most clients will have beefy air conditioning to keep the ambient intake temp and humidity low.

I think 4U servers are quite rare these days, except for models designed to accommodate large numbers of either GPUs or 3.5" hard drives. Most 2-socket servers with up to a few dozen SSDs are 2U designs.

Y'all can try to pry my quad-cpu 3-upi 4U HPE DL.580 from my cold dead hands.

Re: AMD 3rd Gen EPYC Milan Review

#69

Post by derefr »

blagie wrote: post #64
IanCutress wrote: post #50

Earlier quoted context omitted.

AMD is going to keep Zen 2 EPYC sales going for a good while yet. Both families will co-exist in the market.

I suspect so. A lot of the commercial market wants stability. Once I've validated a server config for a particular use, I want to be able to continue building those servers for a long time (often long past obsolescence). That may seem odd, but a lot of safety-critical applications (e.g. medical, military, aerospace, etc.) require spending tens of thousands, hundreds of thousands of dollars, or even millions of dollar…

Rather than buying new-old-stock CPUs, why not just buy all the CPUs the long-term program will ever need when they're still cheap, and stockpile them? It's not like they go bad.

Re: AMD 3rd Gen EPYC Milan Review

#70

Post by mattashii »

IanCutress wrote: post #68
fvv wrote: post #55

Benchmarks https://www.phoronix.com/scan.php?page=article&item=epyc-700...

The article linked at the top has pages of benchmarks. Did.... you miss them?

There are benchmarks, yes, but Anandtechs' bechmarks are mostly synthetic benches from systems almost no-one uses (I don't run SPEC benchmarks daily, and ok, I compile stuff, but not clang, nor using clang)

But Phoronix has synthetic benchmarks from systems quite a few people use (e.g. databases, rendering, simulation). SPEC is nice, but I wouldn't know where to look if I would want to apply that to e.g. postgres. With Phoronix' results, at least there is an idea of how I could apply the results of the benchmark to my usage.

So I find this link quite useful.

That's not to say that I think Anandtechs benchmarks are not valuable (I love reading the nitty gritty details like cache timing specifics), but I can't apply them to anything other than a generic CPU workload, not even slightly in the direction of my specific workload.

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